US 2003/0080802 A1 · Semiconductor integrated circuit device

Abstract

Disclosed is a semiconductor integrated circuit device having a mechanism of compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit constructed by a CMOS; a delay monitor 11 for simulating a critical path of the main circuit constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 13 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 11 and the PN Vt balance compensation circuit 15 and applying a well bias to the delay monitor 11 and the main circuit so as to compensate the operation speed of the delay monitor 11 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.

Claims9

Dependent claims

A semiconductor integrated circuit device comprising:

a control circuit for controlling a well bias of a PMOS transistor and an NMOS transistor, the control circuit being formed in a part of a region for forming a main circuit constructed mainly by a CMOS formed by the PMOS and NMOS transistors during a process of forming said main circuit,
wherein said control circuit has:
means for detecting a deviation of delay time of a critical path having the longest delay time formed in said main circuit from a design parameter and determining said well bias in accordance with the deviation;
and means for detecting a difference between a threshold voltage of said PMOS transistor and a threshold voltage of said NMOS transistor, and said control circuit has a function of correcting said well bias in accordance with the difference output.

1 more element

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device

Life of this patent

Semiconductor integrated circuit device

Life of this patent

Abstract

Claims9