Systems and methods for minimizing harmonic interference
AssigneeGallitzin Allegheny LLC
InventorMasoud Azmoodeh
Life of this patent
Estimating the term…
Abstract
Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed duty cycle while keeping the predetermined frequency.
Claims16
A method for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle, comprising:
- changing the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock;
- and
- generating a low-interference clock having the changed duty cycle while keeping the predetermined frequency.
A system for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and a duty cycle, comprising:
- means for changing the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock;
- and
- means for generating a low-interference clock having the changed duty cycle while keeping the predetermined frequency.
A clock generator, comprising:
- A high frequency clock/oscillator;
- A counter coupled to the clock/oscillator;
- and
- A controller coupled to the down counter to generate a low frequency clock with an asymmetrical duty cycle.
Dependencies are inferred from the claim text.