Mosfet structure with reduced junction capacitance

A MOSFET structure comprising:

• a substrate;
• a tortuous gate on the substrate;
• a gate dielectric layer between the tortuous gate and the substrate;
• a source region and a drain region disposed within the substrate adjacent to the tortuous gate, wherein the source region has a broader part and a narrower part, and the drain region has a broader part and a narrower part, wherein the broader part of the source region is disposed opposite to the narrower part of the drain region, and the narrower part of the source region is disposed opposite to the broader part of the drain region;
• and
• a metal-silicide layer disposed on the tortuous gate and on the source and drain regions.

A metal oxide semiconductor device comprising:

• a substrate;
• a tortuous gate on the substrate;
• a gate dielectric layer between the tortuous gate and the substrate;
• a lightly doped source region, a source region, a lightly doped drain region, and a drain region disposed within the substrate located adjacent to the tortuous gate line, wherein the lightly doped source region, the source region, the lightly doped drain region, and the drain region have a broader part and a narrower part, respectively, wherein the broader part of the lightly doped source region/source region is opposite to the narrower part of the lightly doped drain region/drain region, and the narrower part of the lightly doped source region/source region is opposite to the broader part of the lightly doped drain region/drain region;
• and
• a first metal suicide layer disposed on the tortuous gate and a second metal silicide layer disposed on the source and drain regions.