Vertical transistor and transistor fabrication method
AssigneeInfineon Technologies AG
InventorRolf Weis
Life of this patent
Estimating the term…
Abstract
In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.
Claims15
In a substrate, a vertical transistor comprising:
- a lower doping region disposed in the substrate;
- an upper doping region disposed in the substrate above said lower doping region;
- a channel region disposed between said lower doping region and said upper doping region;
- the substrate defining an isolation trench extending at least to said channel region;
- insulating material filling said isolation trench;
- a lower insulation filling in said isolation trench;
- an upper insulation filling in said isolation trench above said lower insulation filling;
- and
- a conductive layer disposed between said lower insulation filling and said upper insulation filling in said isolation trench.
In a substrate, a vertical transistor comprising:
- a lower doping region disposed in the substrate;
- an upper doping region disposed in the substrate above said lower doping region;
- a channel region disposed between said lower doping region and said upper doping region;
- the substrate defining an isolation trench extending at least to said channel region;
- insulating material filling said isolation trench, said insulating material having:
- a lower insulation filling;
- and
- an upper insulation filling disposed above said lower insulation filling;
- and
- a conductive layer disposed between said lower insulation filling and said upper insulation filling in said isolation trench.
A vertical transistor comprising:
- a substrate defining an isolation trench;
- a lower doping region in said substrate;
- an upper doping region in said substrate above said lower doping region;
- a channel region disposed between said lower doping region and said upper doping region;
- said isolation trench extending at least to said channel region;
- insulating material filling said isolation trench, said insulating material having:
- a lower insulation filling;
- and
- an upper insulation filling disposed above said lower insulation filling;
- and
- a conductive layer disposed between said lower insulation filling and said upper insulation filling in said isolation trench.
A method for fabricating a vertical transistor, which comprises:
- forming a lower doping region in a substrate;
- forming an upper doping region in the substrate above the lower doping region with a channel region being formed between the lower doping region and the upper doping region;
- forming an isolation trench at least next to the channel region;
- forming a lower insulation filling in the isolation trench;
- forming a conductive layer in the isolation trench on the lower insulation filling;
- and
- forming an upper insulation filling in the isolation trench on the conductive layer.
Dependencies are inferred from the claim text.