Tagged address stack and microprocessor using same

A microprocessor, comprising:

• a plurality of data buffers, for storing data specified by load/store addresses;
• a tag address stack (TAS), coupled to said plurality of data buffers, having N entries for storing N unique ones of said load/store addresses, wherein each of said N entries is identified by one of N unique tags;
• a plurality of tag latches, coupled to said TAS, correspondent with said plurality of data buffers, each for storing one of said N unique tags;
• and
• a plurality of tag comparators, coupled to said plurality of tag latches, for comparing said N unique tags stored in said plurality of tag latches.

A method for achieving data coherency in a microprocessor, the method comprising:

• comparing a new memory address with a set of memory addresses, said set being a predetermined size, each of said memory addresses in said set being unique, and wherein a unique tag is associated with each location in said set;
• stalling the microprocessor in response to said comparing, if said new memory address does not match any of said memory addresses in said set and all of said memory addresses are active;
• inserting said new memory address into said set in response to said comparing, if said new memory address does not match any of said memory addresses in said set but at least one of said memory addresses is not active;
• and
• binding to said new memory address said unique tag associated with said location in said set of a matching one of said memory addresses in response to said comparing, if said new memory address matches one of said memory addresses.

A microprocessor having M data buffers for storing data associated with data transfer operations to or from a memory address, comprising:

• an array of N address latches, shared in common by the M data buffers, for storing N unique memory addresses associated with the data transfer operations, wherein N is substantially smaller than M;
• N address comparators, coupled to said array, for comparing said N unique memory addresses with a new memory address of a new data transfer operation;
• and
• control logic, coupled to said N address comparators, for stalling said new data transfer operation until one of said N address latches in said array becomes free, if said control logic determines from said N address comparators that said new memory address is an N+1th unique memory address.