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US 2003/0079104 A1Published application
System and method for addressing memory and transferring data
AssigneeCray Inc.
InventorRoger A. Bethard
Life of this patent
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Abstract
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.
Claims27
An information-handling system, comprising:
- a plurality of processing elements;
- and
- one or more memory sections, wherein each memory section comprises:
- a memory array having a plurality of locations;
- a memory interface operatively connecting the memory array to each of the processing elements;
- and
- a plurality of processor translation look-aside buffers, wherein each processor translation look-aside buffer is operatively coupled to the memory array and to one of the processing elements in order to translate addresses received from the processing elements, and wherein each processor translation look-aside buffer has a plurality of entries, each one of the plurality of entries being used to map a processor address into a memory array address of the memory array.
4 more elements
A method for addressing a memory within a memory system comprising:
- routing a first memory command within the memory system, wherein the first memory command includes a first processor address;
- mapping the first processor address into a first memory address using a mapping function associated with a first processor;
- addressing memory data within the memory system with the first memory address;
- routing a second memory command within the memory system, wherein the second memory command includes a second processor address;
- mapping the second processor address into a second memory address using a mapping function associated with a second processor;
- and
- addressing memory data within the memory system with the second memory array address.
4 more elements
An information-handling system comprising:
- a memory;
- and
- a plurality of processing elements, wherein each of the processing elements is operatively coupled to the memory,
- wherein the memory includes mapping means for mapping processor addresses received from the processing elements into memory addresses in the memory, and wherein the mapping means includes a first mapping function for translating processor addresses associated with a first processing element and a second mapping function for translating processor addresses associated with a second processing element.
1 more element
An information-handling system, comprising:
- a plurality of processing elements;
- and
- a memory having a first memory section, wherein the first memory section is operatively coupled to each processing element, and wherein the first memory section comprises:
- a memory array;
- a memory interface operatively connecting the memory array to each of the processing elements;
- and
- a block transfer engine operatively coupled to the memory array, wherein the block transfer engine operates under command of one of the processing elements to transfer data from a memory location that cannot be addressed by the processing element to a memory location that can be addressed by the processing element.
4 more elements
A method for transferring data in a memory comprising:
- creating a block transfer command in a processor, wherein the block transfer command includes an amount of transfer data, a source transfer address, and a destination transfer address, wherein the source transfer address is a non processor-addressable memory address, and wherein the destination transfer address is a processor-addressable memory address;
- routing the block transfer command from the processor to the memory;
- and
- transferring the amount of transfer data from the source transfer address to the destination transfer address.
1 more element
An information-handling system comprising:
- a memory;
- and
- a plurality of processing elements, wherein each of the processing elements is operatively coupled to the memory,
- wherein the memory includes transferring means for transferring data from a memory location in the memory that cannot be addressed by the processing elements to a memory location that can be addressed by the processing elements.
1 more element
A system comprising:
- a first information-handling system, the first information-handling system comprising:
- a plurality of first processing elements;
- and
- a first memory section, wherein the first memory section is operatively coupled to each of the first processing elements, and wherein the first memory section comprises:
- a first memory array;
- a first memory interface associated with the first memory array;
- and
- a first block transfer engine operatively coupled to the first memory array, wherein the first block transfer engine is associated with each of the first processing elements through the first memory interface;
- a second information-handling system, the second information-handling system comprising:
- a plurality of second processing elements;
- and
- a second memory section, wherein the second memory section is operatively coupled to each of the second processing elements, and wherein the second memory section comprises:
- a second memory array;
- a second memory interface associated with the second memory array;
- and
- a second block transfer engine operatively coupled to the second memory array, wherein the second block transfer engine is associated with each of the second processing elements through the second memory interface;
- and
- a communications channel connecting the first and second information-handling systems,
- wherein the second block transfer engine transfers an amount of data from a first memory address in the second memory array to a second memory address in the first memory array over the communications channel.
16 more elements
A method for transferring data in a system comprising:
- creating a block transfer command in a processor of a first information-handling system, wherein the block transfer command includes an amount of transfer data, a source transfer address, and a destination transfer address, wherein the source transfer address is a first memory address of a first memory of the first information-handling system, and wherein the destination transfer address is a second memory address of a second memory of a second information-handling system;
- routing the block transfer command from the processor to the first memory of the first information-handling system;
- and
- transferring the amount of transfer data from the source transfer address to the destination transfer address.
1 more element
A system comprising:
- a first information-handling system comprising a first memory and a plurality of first processing elements, wherein each of the first processing elements is operatively coupled to the first memory;
- a second information-handling system comprising a second memory and a plurality of second processing elements, wherein each of the second processing elements is operatively coupled to the second memory;
- and
- means for transferring data from a first memory space of the first memory to a second memory space of the second memory.
1 more element
Dependencies are inferred from the claim text.