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US 2003/0076902 A1Published application
System and method for DC offset compensation and bit synchronization
AssigneeBroadcom Corporation
InventorRebecca Yuan
Life of this patent
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Abstract
A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.
Claims28
A method for operating a wireless device, the method comprising:
- receiving a data signal;
- accumulating a first sample sum value for a first set of DC compensated samples of the received data signal, the first set of DC compensated samples corresponding to a first timing hypothesis;
- accumulating a second sample sum for a second set of DC compensated samples of the received data signal, the second set of DC compensated samples corresponding to a second timing hypothesis;
- accumulating a third sample sum value for a third set of DC compensated samples of the received data signal, the third set of DC compensated samples corresponding to a third timing hypothesis;
- computing a first averaged sample sum using the first sample sum;
- computing a second averaged sample sum using the second sample sum;
- computing a third averaged sample sum using the third sample sum;
- identifying the maximum of the first averaged sample sum, the second averaged sample sum, and the third averaged sample sum;
- and
- generating an output symbol corresponding to the identified maximum;
7 more elements
An electronic device comprising:
- a DC offset compensator;
- a plurality of sample accumulators, each of the plurality of sample accumulators being coupled with the DC offset compensator;
- and
- a maximum identifier coupled with each of the plurality of sample accumulators;
- wherein the maximum identifier is configured to identify the maximum output of the plurality of sample accumulators and cause an output to be generated according to the identified maximum output.
2 more elements
An apparatus comprising:
- means for receiving a data signal;
- means for accumulating a first sample sum for a first set of samples of the received data signal, the first set of samples corresponding to a first timing hypothesis;
- means for accumulating a second sample sum for a second set of samples of the received data signal, the second set of samples corresponding to a second timing hypothesis;
- means for accumulating a third sample sum for a third set of samples of the received data signal, the third set of samples corresponding to a third timing hypothesis;
- means for computing a first averaged sample sum using the first sample sum;
- means for computing a second averaged sample sum using the second sample sum;
- means for computing a third averaged sample sum using the third sample sum;
- means for identifying the maximum of the first averaged sample sum, the second averaged sample sum, and the third averaged sample sum;
- and
- means for outputting a symbol corresponding to the identified maximum;
- wherein the output symbol is a first value when the sample sum corresponding to the identified maximum is positive.
8 more elements
An electronic device comprising:
- a receiver module;
- an analog-to-digital converter connected with the receiver module;
- a DC tracking loop connected to the analog-to-digital converter;
- and
- a multi-hypothesis bit synchronizer (MHBS) connected to the DC tracking loop.
2 more elements
Dependencies are inferred from the claim text.