US 2003/0076831 A1 · Mechanism for packet component merging and channel assignment, and packet decomposition and channel reassignment in a multiprocessor system

Abstract

A technique efficiently combines data and ordered transactions in a multiprocessor system having a plurality of nodes interconnected by a hierarchical switch. The technique further enables an ordered channel of the system to make progress in the presence of a blocked interface within the hierarchical switch. Specifically, the technique combines ordered components and unordered data components into common packets that are transmitted over an ordered channel of the system in the event that ordered and unordered components are generated simultaneously. The technique further allows, in the event that a combined packet in the ordered channel is stalled due to a data buffer dependency, the packet to be decomposed into an ordered component and an unordered data component wherein the ordered component remains in the ordered channel and the unordered data component is reassigned to the unordered data channel.

Claims17

Dependent claims

A method for efficiently transmitting packets within a multiprocessor computer system having a plurality of multiprocessor nodes interconnected by a switch fabric, the system having one or more ordered virtual channels and one or more unordered virtual channels configured to carry request and response packets among the multiprocessor nodes, the method comprising the steps of:

providing at a first node at least one ordered queue for storing packets subject to an ordering requirement in the multiprocessor computer system;
providing at the first node at least one unordered buffer for storing packets which are not subject to an ordering requirement;
receiving at the first node a single, common packet that includes both an ordered component and an unordered component;
determining whether available space exists at the ordered queue and at the unordered buffer;
if available space exists at the ordered queue, but not at the unordered buffer, decomposing the single, common packet into a separate ordered component and a separate unordered component;
and
placing the separate ordered component that was decomposed from the single, common packet into the ordered queue, thereby allowing the ordered virtual channel to progress.

4 more elements

combining an ordered response component with an unordered response component to form a single, combined response packet;
placing the single, combined response packet into an ordered virtual channel for transmission to a requesting processor;
detecting a stall condition at the ordered virtual channel into which the single, combined response packet was placed;
in response to detecting the stall condition, decomposing the single, combined response packet back into a separate ordered response component and a separate unordered response component;
and
placing the decomposed unordered response component into an unordered virtual channel for transmission to the requesting processor, thereby permitting the unordered component to progress through the system despite the stall condition at the ordered virtual channel.

3 more elements

Dependencies are inferred from the claim text.

Mechanism for packet component merging and channel assignment, and packet decomposition and channel reassignment in a multiprocessor system

Life of this patent

Mechanism for packet component merging and channel assignment, and packet decomposition and channel reassignment in a multiprocessor system

Life of this patent

Abstract

Claims17