Semiconductor device
AssigneeHitachi, Ltd.
InventorsMasanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
Life of this patent
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Abstract
The present invention relates to a system LSI consolidating a logic circuit and an SRAM circuit. More specifically, the present invention relates to a semiconductor device which can reduce a leakage current and the power consumption in the standby state. The logic circuit in the system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing a leakage current. At the same time, the SRAM circuit controls a substrate bias to reduce the leakage current.
Claims15
A semiconductor device comprising:
- a logic circuit including a plurality of MIS transistors;
- a first switch connected between an operating voltage supply point of the MIS transistor in said logic circuit and a power line;
- a memory array including a plurality of static memory cells;
- and
- a control circuit changing the substrate voltage of the MIS transistor constructing said memory cell according to its state.
A semiconductor device comprising:
- a first memory cell having a first MIS transistor, a second MIS transistor, a third MIS transistor and a fourth MIS transistor, which are of an N channel type;
- a second memory cell having a fifth MIS transistor, a sixth MIS transistor, a seventh MIS transistor and an eighth MIS transistor, which are of an N channel type,
- wherein the gate-insulating film thickness of said first MIS transistor is smaller than that of said fifth MIS transistor.
A semiconductor device comprising:
- a plurality of memory cells arranged at the cross point of a plurality of wordlines and bitlines;
- a read/write control circuit connected to said bitline;
- a decoder selecting said wordline;
- a first switch connected between said decoder and a first node;
- and
- a second switch connected between said read/write control circuit and a second node.
Dependencies are inferred from the claim text.