Semiconductor memory device having first and second memory architecture and memory system using the same

A memory system comprising:

• a memory controller;
• a first memory module connected to the memory controller via data bus lines and including i memory devices;
• and
• a second memory module connected to the memory controller via the data bus lines and including i/2 memory devices,
• wherein each of the memory devices of each of the first and second memory modules comprises:
• a first memory architecture having p memory banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the memory banks, and n/2 data terminals DQ;
• and
• a second memory architecture having p memory banks, a page size of m bytes, and n data terminals DQ,
• wherein the first memory architecture is selected by the memory devices of the first memory module, and the second memory architecture is selected by the memory devices of the second memory module.

A memory system comprising:

• a memory controller;
• a first memory module connected to the memory controller via data bus lines and including i memory devices;
• and
• a second memory module connected to the memory controller via the data bus lines and including i/2 memory devices,
• wherein each of the memory devices of each of the first and second memory modules comprises:
• a first memory architecture having p memory banks, a page size of m/2 bytes of m/2 memory cells connected to one word line in each of the memory banks, and n/2 data terminals DQ;
• and
• a second memory architecture having p/2 memory banks, a page size of m bytes, and n data terminals DQ,
• wherein the first memory architecture is selected by the memory devices of the first memory module, and the second memory architecture is selected by the memory devices of the second memory module.