Stack element circuit
AssigneeSaifun Semiconductors Ltd.
InventorsJoseph S. Shor, Eduardo Maayan
Life of this patent
Estimating the term…
Abstract
A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.
Claims43
A circuit comprising:
- a reference element adapted to provide a reference current and having a control terminal and a first terminal there being a voltage (Vct) between said control terminal and said first terminal of said reference element;
- and
- a plurality of series-connected stack elements, each said stack element comprising a first terminal connected to a first voltage, and a control terminal connected to a second terminal, said stack elements being adapted to receive at least one of said reference current and a multiple of said reference current, said stack elements and said reference element being matched such that a voltage between said control terminal and said first terminal of at least one of said stack elements is generally the same as Vct.
12 The circuit according to claim 9 wherein an input of said reference element is at ground (GND).
A driver comprising:
- first and second PMOS transistors, first and second NMOS transistors, and first and second current sources, wherein a gate and a drain of said first PMOS transistor are connected to said first current source, and said first current source is grounded;
- and wherein a source of said first PMOS transistor is connected to a source of said first NMOS transistor, said first NMOS transistor having its gate and its drain connected to said second current source, said second current source being connected to a supply voltage;
- and wherein gates of said NMOS transistors are connected to each other, and gates of said PMOS transistors are connected to each other;
- and wherein a drain of said second NMOS transistor is connected to said supply voltage and a source of said second NMOS transistor is connected to an output of said driver;
- and wherein a drain of said second PMOS transistor is connected to GND, and a source of said second PMOS transistor is connected to the output of said driver.
A circuit comprising:
- a reference element adapted to receive a first reference voltage and provide a reference current;
- and
- a plurality of series-connected stack elements adapted to receive said reference current and provide a multiple of said first reference voltage, wherein said multiple is a function of the number of said stack elements.
Dependencies are inferred from the claim text.