Semiconductor device having line-and-space pattern group

A semiconductor device comprising:

• a semiconductor substrate;
• a first memory cell array having a plurality of first gate wirings in parallel with each other formed on the semiconductor substrate and separated from each other by an interval and respectively having a first width;
• a first selective transistor having a second gate wiring with a second width different from the first width and formed on the semiconductor substrate adjacent to the first memory cell array in parallel with the first gate wirings;
• a second selective transistor having a third gate wiring formed on the semiconductor substrate adjacent to the first memory cell array on the same side as the first selective transistor with respect to the first memory cell array on an extension line of the second gate wiring;
• and
• a dummy pattern formed adjacent to the first memory cell array between the second gate wiring and the third gate wiring in parallel with the first gate wirings and having a width equal to the second width.