Thin, thermally enhanced flip chip in a leaded molded package
AssigneeFairchild Semiconductor Corporation
InventorsRajeev Joshi, Chung-Lin Wu
Life of this patent
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Abstract
Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
Claims15
A semiconductor die package comprising:
- (a) a semiconductor die including a first surface and a second surface;
- (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface;
- (c) a gate lead structure being coupled to the first surface;
- and
- (d) a molding material around the source lead structure and the semiconductor die, wherein the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.
A semiconductor die package comprising:
- a) a semiconductor die comprising an RF VDMOS transistor including a source region, a gate region, and a drain region;
- b) a source lead structure including a protruding portion having a major surface, and a plurality of leads extending laterally away from the protruding region, wherein the source lead structure is coupled to the source region of the semiconductor die;
- c) a gate lead structure coupled to the gate region of the semiconductor die;
- and
- d) a molding material covering at least a portion of the source lead structure, the gate lead structure and the semiconductor die,
- wherein the major surface of the protruding portion is exposed through the molding material.
A method for forming a semiconductor die package, the method comprising:
- (a) attaching a semiconductor die including a first surface and a second surface, and solder on the first surface to a lead frame structure including a source lead structure having a protruding portion with a major surface, and a gate lead structure;
- and
- (b) molding a molding material around the semiconductor die and the source and the gate lead structures, wherein the second surface of the semiconductor die and the major surface of the source lead structure are exposed through the molding material.
Dependencies are inferred from the claim text.