Thin film transistor array panel having a means for visual inspection and a method of performing visual inspection

A thin film transistor panel comprising:

• an insulating substrate having a display area and a surrounding area;
• a plurality of gate lines formed on the insulating substrate;
• a data driving signal line formed on the surrounding area of the insulating substrate;
• a data inspection signal line formed on the surrounding area of the insulating area;
• a gate insulating layer formed on the gate lines, the data driving signal line and the data inspection signal line;
• a first semiconductor pattern formed on the gate insulating layer, at least a portion thereof overlapping the data driving signal lines;
• first and second ohmic contact layers formed on the first semiconductor pattern, exposing therebetween a portion of the first semiconductor pattern corresponding to the data driving signal line;
• a plurality of data lines formed on the gate insulating layer and intersecting the gate lines to define the display area, at least a portion thereof being formed on the second ohmic contact layer;
• a first electrode for inspection formed on the gate insulating layer, at least a portion thereof being formed on the first ohmic contact layer;
• a passivation layer formed on the data lines and the first electrode for inspection;
• and
• a first connection portion formed on the passivation layer and connecting the data inspection signal line and the first electrode for inspection.

A method of manufacturing a thin film transistor panel comprising:

• a first step of forming a gate line, a data inspection signal line and a data driving signal line;
• a second step of depositing a gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductive layer;
• a third step of patterning the conductive layer, the ohmic contact layer and the semiconductor layer using photo-etching once to form a data line, a first electrode for inspection, an ohmic contact layer pattern under the first electrode for inspection and the data line, a semiconductor layer pattern under the ohmic contact layer pattern;
• a fourth step of forming a passivation layer on the data line and the first electrode for inspection;
• and
• a fifth step of forming a first connection portion connecting the data inspection signal line and the first electrode for inspection.

A thin film transistor panel comprising:

• an insulating comprising a display area and a surrounding area;
• a plurality of gate lines formed on the insulating substrate;
• a plurality of data lines formed on the insulating substrate and intersecting the gate lines to define the display area;
• a gate driving circuit formed on the surrounding area and connected to the gate lines;
• and
• a logic circuit for visual inspection (VI) inserted between the gate driving circuit and the gate lines and having a plurality of first to third NOR gates,
• wherein a first input terminal of the first NOR gate of the logic circuit for visual inspection is connected to an output terminal of the gate driving circuit and a second input terminal thereof is connected to a CON1 terminal and an output terminal thereof is connected to a first input terminal of the second or the third NOR gate, and a second input terminal of the second NOR gate is connected to a CON2 terminal and an output terminal thereof is connected to the gate lines in odd number, and a second input terminal of the third NOR gate is connected to a CON3 terminal and an output terminal thereof is connected to the gate lines in even number.

A method of performing visual inspection in a liquid crystal display including a first insulating substrate having a display area and a surrounding area, a plurality of gate lines formed on the first insulating substrate, a plurality of data lines formed on the first insulating substrate and intersecting the gate lines to define the display area, a pixel thin film transistor formed on the first insulating substrate and connected to the gate lines and the data lines, a pixel electrode formed on the display area and connected to the pixel thin film transistor, a gate driving circuit formed on the surrounding area of the thin film transistor and connected to the gate lines and having first and second clock signal terminals, an on and off power terminal and a scan start terminal, a driving signal line formed on the surrounding area of the first insulating substrate and a driving signal terminal, an inspection signal line on the surrounding area of the first insulating substrate and an inspection signal terminal, a thin film transistor for inspection having a drain electrode coupled to the data lines, a source electrode coupled to the inspection signal line and a gate electrode coupled to the driving signal line, a common voltage terminal formed on the surrounding area of the first insulating area, a second insulating substrate disposed opposite the first insulating substrate, a common electrode formed on the second insulating substrate and connected to the common voltage terminal, and a liquid crystal material injected between the first and the second insulating substrates,

• wherein, the method of performing visual inspection comprises applying Von voltages to the first and second clock signal terminals of the gate driving circuit, the on and off power terminal, the scan start terminal and the driving signal terminal, and applying a common voltage to the common voltage terminal.

A method of performing visual inspection in a liquid crystal display including a first insulating substrate having a display area and a surrounding area, a plurality of gate lines formed on the first insulating substrate, a plurality of data lines formed on the first insulating substrate and intersecting the gate lines to define the display area, a pixel thin film transistor formed on the first insulating substrate and connected to the gate lines and the data lines, a pixel electrode formed on the display area and connected to the pixel thin film transistor, a gate driving circuit formed on the surrounding area of the thin film transistor and connected to the gate lines and having first and second clock signal terminals, an on and off power terminal and a scan start terminal, a short strip formed on the surrounding area of the first insulating area and connected to the data lines, a common voltage terminal formed on the surrounding area of the first insulating area, a second insulating substrate disposed opposite the first insulating substrate, a common electrode formed on the second insulating substrate and connected to the common voltage terminal, and a liquid crystal material injected between the first and the second insulating substrates,

• wherein, the method of performing visual inspection comprises applying Von voltages to the first and second clock signal terminals of the gate driving circuit, the on and off power terminal, the scan start terminal and the driving signal terminal, and applying an inspection signal to the short strip and applying a common voltage to the common voltage terminal.