Radar-guided missile programmable digital predetection signal processor

In a missile-based radar guidance system comprising a multi-channel guidance signal input for inputting a missile-generated guidance signals and an analog to digital converter for digitizing said guidance signals, a system for processing said guidance signals, comprising:

• a plurality of programmable digital filters for independently filtering said digitized guidance signals;
• a dual path processor for processing said filtered guidance signals and having a serial output;
• a power estimator for estimating power of said filtered guidance signals;
• and
• a programmable digital threshold detector for performing calculations based on said filtered guidance signals to determine if said guidance signal power on each of said system channels is within a predetermined threshold window;
• said power estimator, said digital threshold detector and said dual path processor each performing processing functions based on common guidance signal inputs;
• said digital filters, said power estimator, said digital threshold detector and said dual path processor being implemented together in a single monolithic package.

A circuit for performing base 10 logarithmic calculations of a binary signal in a digital system to optimize system performance, said circuit comprising:

• a priority encoder for determining a most significant bit position of said binary number, said most significant bit representing a base 2 logarithmic integer component of said input binary signal;
• a decimal selector for selecting a predetermined number of bits to follow said base 2 logarithmic integer component determined by said priority encoder, said predetermined number of bits representing a base 2 logarithmic fractional component following said integer component of said input binary signal;
• an adder for combining said integer component with said fractional component to thereby output a base 2 logarithmic value of said input binary signal;
• and
• a multiplier for dividing said base 2 logarithmic value of said input binary signal by a base 2 logarithmic value of 10 and to thereby output a base 10 logarithmic value of said input binary signal.

A method of calculating base 10 logarithmic values of a binary signal in a digital system to optimize system performance, said method comprising:

• determining a most significant bit position of said binary signal, said most significant bit representing a base 2 logarithmic integer component of said input binary signal;
• selecting a predetermined number of bits to follow said base 2 logarithmic integer component, said predetermined number of bits representing a base 2 logarithmic fractional component following said integer component of said binary signal;
• combining said integer component with said fractional component to thereby output a base 2 logarithmic value of said binary signal;
• and
• dividing said base 2 logarithmic value of said binary signal by a base 2 logarithmic value of 10 to thereby output a base 10 logarithmic value of said binary signal.