Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShinichi Kimura, Hiroyuki Tsujikawa
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Abstract
With respect to layout data of a semiconductor integrated circuit, a latch-up verifying operation is carried out in high precision. In a latch-up verifying method, a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information.
Claims28
A latch-up verifying method, comprising the steps of:
- extracting a well region, at least one transistor region, and at least one substrate contact region from layout data of a semiconductor integrated circuit to be formed on a semiconductor substrate;
- setting an over-sizing value for at least one of said at least one transistor region and/or at least one of said at least one substrate contact region based upon the extracted information;
- and
- executing latch-up verification of the layout data utilizing the separately set over-sizing value.
A latch-up verifying method, comprising the steps of:
- extracting a well region, at least one transistor region, and at least one substrate contact region from layout data of a semiconductor integrated circuit to be formed on a semiconductor substrate;
- sequentially executing steps for separately setting respective over-sizing values for at least one of the transistor region and at least one of the substrate contact region based upon the extracted information;
- and
- executing latch-up verification of the layout data utilizing the separately set over-sizing value.
A latch-up verifying apparatus including:
- means for extracting a well region, at least one transistor region, and at least one substrate contract region from layout data of a semiconductor integrated circuit formed on a semiconductor substrate;
- and
- means for sequentially, separately setting over-sizing values for at least two of the transistor and substrate contact regions based upon the extracted information;
- and
- means for executing latch-up verification of the layout data utilizing the separately set over-sizing values.
A latch-up verifying apparatus including:
- means for extracting a well region, at least one transistor region, and at least one substrate contact region from layout data of a semiconductor integrated circuit formed on a semiconductor substrate;
- and
- means for setting an over-sizing value for at least one of said at least one transistor region and/or at least one of said at least one substrate contact region based upon the extracted information;
- and
- means for executing latch-up verification of the layout data utilizing the separately set over-sizing values.
A latch-up verifying apparatus including:
- means for extracting a well region, at least one transistor region, and at least one substrate contact region from layout data of a semiconductor integrated circuit formed on a semiconductor substrate;
- and
- means of sequentially, separately setting over-sizing values for at least one of the transistor region and at least one of the substrate contact region based upon the extracted information;
- and
- means for executing latch-up verification for the layout data utilizing the separately set over-sizing values.
Dependencies are inferred from the claim text.