Configurable prioritization of core generated interrupts

A microprocessor for handling interrupts, the microprocessor receiving first interrupts from an interrupt controller, the microprocessor comprising:

• a core, for executing instructions, said core generating second interrupts;
• priority storage means coupled to said core, for storing programmable priorities for said second interrupts;
• and
• a priority encoder, coupled to said core, and to said priority storage means, for receiving the first and said second interrupts, and for prioritizing the first and said second interrupts utilizing said programmable priorities stored in said priority storage means.

A method for prioritizing on-core and off-core interrupts within a processing system, comprising:

• receiving the off-core interrupts;
• receiving the on-core interrupts, the on-core interrupts having programmable priority levels;
• sorting the received off-core and on-core interrupts according to their priority levels;
• and
• producing an indication of which of the received off-core and on-core interrupts has the highest priority.

A computer program product for use with a computing device, the computer program product comprising:

• a computer usable medium, having computer readable program code embodied in said medium, for causing a microprocessor to be described, said computer readable program code comprising:
• first program code for providing an interrupt priority encoder for prioritizing between core generated interrupts and non-core generated interrupts;
• and
• second program code for providing an interrupt vector generator, for receiving an indication from the priority encoder of a highest priority interrupt, and for generated an interrupt vector for the highest priority interrupt.

A computer data signal embodied in a transmission medium comprising:

• computer-readable program code for providing a microprocessor for handling both internally generated and externally generated interrupts, said program code comprising:
• first program code for providing a programmable offset storage register for storing a programmable offset;
• second program code for providing a plurality of interrupt priority level fields that store programmed priority levels for the internally generated interrupts;
• third program code for providing a priority encoder, the encoder prioritizing between the internally generated and externally generated interrupts utilizing the programmed priority levels to select an interrupt with the highest priority, the encoder providing an indication of the interrupt with the highest priority;
• and
• fourth program code for providing a vector generator for generating an interrupt vector for the interrupt with the highest priority, the vector generator utilizing the programmable offset to calculate the interrupt vector.