System and method of testing non-volatile memory cells

A method of testing a non-volatile floating gate memory cell comprising:

• placing the memory cell in a low threshold voltage, Vt, state;
• applying a reduced drain voltage to a drain of the memory cell;
• applying a nominal or elevated gate voltage to a control gate of the memory cell;
• and
• comparing a drain current of the memory cell to a reference drain current, wherein the memory cell is determined to be defective if the drain current is below the reference current.

A method of testing a non-volatile floating gate memory cell comprising:

• placing the memory cell in a low threshold voltage, Vt, state;
• applying a drain voltage in the range of 0.5 to 2.5 volts to a drain of the memory cell;
• applying a gate voltage in the range of 2.0 to 12 volts to a control gate of the memory cell;
• and
• comparing a drain current of the memory cell to a reference drain current in the range of 10 μA to 200 μA, wherein the memory cell is determined to be defective if the drain current is below the reference current.

A method of testing a non-volatile floating gate memory cell comprising:

• placing the memory cell in a low threshold voltage, Vt, state;
• applying a drain voltage of about 0.8 volts to a drain of the memory cell;
• applying a gate voltage of about 7 volts to a control gate of the memory cell;
• and
• comparing a drain current of the memory cell to a reference drain current of about 60 μA, wherein the memory cell is determined to be defective if the drain current is below the reference current.

A method of testing a non-volatile floating gate memory cell comprising:

• placing the memory cell in a low threshold voltage, Vt, state;
• applying a drain voltage in the range of 0.1 to 1.0 volts to a drain of the memory cell;
• applying a gate voltage in the range of 0.0 to 12 volts to a control gate of the memory cell;
• and
• comparing a drain current of the memory cell to a reference drain current in the range of 1 μA to 100 μA, wherein the memory cell is determined to be defective if the drain current is below the reference current.

A method of testing a non-volatile floating gate memory cell comprising:

• placing the memory cell in a low threshold voltage, Vt, state;
• applying a drain voltage of about 0.5 volts to a drain of the memory cell;
• applying a gate voltage of about 4 volts to a control gate of the memory cell;
• and
• comparing a drain current of the memory cell to a reference drain current of about 40 μA, wherein the memory cell is determined to be defective if the drain current is below the reference current.

A method of testing a flash memory comprising:

• reading erased memory cells using a first reference current;
• increasing a gate voltage coupled to the erased memory cells;
• reading the erased memory cells having an increased gate voltage using a second reference current, where the second reference current is greater than the first reference current;
• and
• identifying memory cells as defective if the erased memory cell is read as being programmed while using the second reference current.

A method of testing a flash memory comprising:

• coupling a first drain voltage to erased memory cells;
• reading the erased memory cells by comparing a bit line current to a reference current;
• coupling a second drain voltage that is less than the first drain voltage to the erased memory cells;
• reading the erased memory cells by comparing the bit line current to the reference current;
• and
• identifying memory cells as defective if the drain current is less than the reference current while using the second drain voltage.