Non-volatile memory with block erase
AssigneeMicron Technology, Inc.
InventorBrady L. Keays
Life of this patent
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Abstract
A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block to erase the remaining rows. In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.
Claims10
A flash memory device comprising:
- a memory array having a plurality of erasable blocks of memory cells, wherein the memory cells in each block are arranged in rows;
- and
- a control circuit to control memory operations to the memory array, wherein the control circuit applies a first number of erase pulses to a block being erased in a first stage and a second number of erase pulses to the block in a second stage, further wherein the second number of erase pulses applied in the second stage is based on the number of erase pulses needed in the first stage to verify a predetermined number of rows in the block have been erased.
A method for erasing a flash memory device having a plurality of blocks of memory cells, each block arrange arranged in rows of cells, a register array, and a controller coupled to and controlling the memory cells and the register array, the method comprising:
- the controller applying a first number of erase pulses to a first block of memory cells, of the plurality of blocks of memory cells, being erased in a first stage;
- the controller applying a second number of erase pulses to the first block of memory cells in a second stage wherein the second number of erase pulses is based on the first number of erase pulses needed to verify a predetermined number of rows in the first block have been erased;
- and
- the controller updating the register array to reflect which rows of cells on the first block of memory cells has been verified as erased.
Dependencies are inferred from the claim text.