Scheme to improve performance of timing recovery systems for read channels in a disk drive
AssigneeAgere Systems Inc.
InventorViswanath Annampedu
Life of this patent
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Abstract
A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.
Claims23
A digital phase lock loop circuit comprising:
- an error generation circuit for generating at least three error signals;
- and,
- a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
A read channel device comprising:
- an error generation circuit for generating at least three error signals;
- and,
- a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
A data storage system comprising:
- a data storage assembly;
- a read channel device operable to read information stored on the data storage assembly, said read channel device comprising an error generation circuit for generating at least three error signals;
- and, a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals.
A method for determining and correcting a phase error, comprising the steps of:
- generating at least three error signals;
- and,
- generating at least one phase error adjustment signal from the at least three error signals.
Dependencies are inferred from the claim text.