Integrated circuit with a MOS structure having reduced parasitic bipolar transistor action

A quasi-vertical double diffused metal oxide semiconductor (DMOS) transistor for an integrated circuit comprising:

• a substrate having a surface;
• one or more perimeter body regions formed in the substrate proximate the surface of the substrate, each of the perimeter body regions is of the first conductivity type;
• a source of a second conductivity type with a high doping density formed in atl least one body region;
• and
• a layer of narrow band gap material positioned adjacent the surface of the substrate and the body regions, the narrow band gap material having a band gap narrower than a maximum band gap of the body regions, wherein at least a portion of each source is formed in the layer of narrow band gap material.

A lateral DMOS transistor for an integrated circuit comprising:

• a substrate of a first conductivity type with a low doping concentration having a surface;
• a drain contact of a second conductivity type with a high doping concentration formed in the substrate adjacent the surface of the substrate;
• a gate positioned on the surface of the substrate;
• a body of the first conductivity type formed in the substrate adjacent the surface of the substrate;
• a source of the second conductivity type with high doping density formed in the body, wherein the gate is positioned in between the source and the drain contact;
• and
• a layer of narrow band gap material positioned in a surface portion of the body and at least a portion of the source, the layer of narrow band gap material having a narrower band gap than the band gap of the substrate.

A method of forming a MOS device in an integrated circuit, the method comprising:

• forming a body region in a substrate adjacent a surface of the substrate;
• forming a source in the body region;
• and
• forming a layer of narrow band gap material adjacent the surface of the substrate, the layer of narrow band gap material having a band gap narrower than a band gap of the substrate material, wherein at least a portion of the source is within the layer of narrow band gap material.

A method of forming a quasi-vertical DMOS for an integrated circuit, the method comprising:

• forming a patterned first dielectric layer on the surface of a substrate, wherein a first portion of the surface of the substrate is exposed by the pattern;
• forming a layer of narrow band gap material on the exposed first portion of the surface of the substrate, wherein the layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate;
• forming a second dielectric layer on the narrow band gap material;
• depositing a gate proximate a medial portion of the second dielectric layer;
• forming a pair of perimeter body regions in the substrate, wherein the gate is positioned between the perimeter body regions;
• and
• forming a source in each body region, wherein at least apportion of the source is also formed in the layer of narrow band gap material.

A method of forming a quasi-vertical DMOS for an integrated circuit, the method comprising:

• forming patterned first dielectric layer on a surface of a substrate having a first portion of the surface of the substrate exposed by the pattern;
• forming a layer of gate dielectric on the exposed first portion of the surface of the substrate;
• depositing a gate proximate a medial portion of the layer of gate dielectric;
• forming a pair of perimeter body regions in the substrate, wherein the gate is positioned between the perimeter body regions;
• forming layers of narrow band gap material in portions of the body regions, wherein the layers of narrow band gap material have a narrower band gap than the band gap of the remaining portions of the body regions;
• and
• forming a source in each body region, wherein at least apportion of the source is also formed in the layer of narrow band gap material.

A method of forming a lateral DMOS for an integrated circuit, the method comprising:

• forming a body of a first conductivity type in a substrate of a first conductivity type with a low doping density, wherein the body is positioned adjacent a surface of the substrate;
• forming a layer of narrow band gap material on the surface of the substrate adjacent the body, wherein the layer of narrow band gap material has a band gap that is narrower than the band gap of the body;
• and
• forming a source of a second conductivity type with a high doping density in the body, wherein at least a portion of the source is formed in the layer of narrow band gap material, further wherein the narrow band gap material suppresses carrier injection from the source into the body thereby reducing parasitic HFE.

A vertical DMOS device comprising:

• a substrate;
• at least one gate;
• a dielectric layer insulating each gate from the substrate;
• a drain region formed in the substrate;
• at least one body region formed in the substrate adjacent the drain region and proximate a working surface of the substrate;
• a layer of narrow band gap material formed in each body region adjacent the surface of the substrate, wherein the layer of narrow band gap material has a narrower band gap than the band gap of the remaining portions of the body region;
• and
• a source formed in each body region, wherein at least a portion of each source is also formed in the layer of narrow band gap material.

A method of forming a vertical DMOS comprising:

• forming a drain region in a substrate of a first conductivity type with a low dopant density;
• forming a body region in the substrate of a second conductivity type over the drain region;
• forming a layer of narrow band gap material in the substrate, wherein the layer of narrow band gap material has a narrower band gap than portions of the body region;
• forming at least one source region of the first conductivity type with high dopant density in the body, wherein at least a portion of each source region is formed in the layer of narrow band gap material;
• and
• forming at least one gate.

A switching power supply control circuit comprising:

• a diode bridge to perform full rectification of the input AC voltage;
• a transformer coupled to the diode bridge to provide galvanic isolation and voltage conversion;
• a quasi-vertical DMOS transistor coupled to control the voltage through the transformer;
• control circuitry coupled to a gate of the quasi-vertical DMOS transistor to switch the DMOS transistor on and off, wherein the control circuitry controls a duty cycle of the DMOS transistor to achieve a desired output from the transformer;
• and
• wherein the quasi-vertical DMOS transistor comprises,
• a substrate of a first conductivity type with a low doping density having a surface, wherein the gate is formed overlaying the surface of the substrate,
• one or more body regions formed in the substrate proximate the surface of the substrate, each of the body regions is of the first conductivity type,
• a source of a second conductivity type with a high doping density formed in each body region, wherein each source and each body are positioned proximate an associated edge of the gate, and
• a layer of narrow band gap material positioned adjacent the surface of the substrate and the body regions, the narrow band gap material having a band gap narrower than the semiconductor material of the body.

A solid state relay integrated circuit comprising:

• a photo diode stack to drive a voltage having a first output and a second output;
• a first high voltage lateral DMOS having a gate, source and drain, the gate of the first high voltage DMOS is coupled to the first output of the photo diode stack, the source of the first high voltage DMOS is coupled to the second output of the photo diode stack;
• a second high voltage lateral DMOS having a gate, source and drain, the gate of the second high voltage lateral DMOS is coupled to the first output of the photo diode stack, the source of the second high voltage lateral DMOS is coupled to the second output of the photo diode stack;
• and
• wherein the first and second high voltage lateral DMOS comprise,
• a substrate of a first conductivity type with a low doping concentration having a surface,
• a drain contact of a second conductivity type with a high doping density formed in the substrate adjacent the surface of the substrate,
• a gate positioned on the surface of the substrate,
• a body of the first conductivity type formed in the substrate adjacent the surface of the substrate,
• a source of the second conductivity type with high doping concentration formed in the body adjacent a surface of the substrate, wherein the gate is positioned in between the source and the drain contact, and
• a layer of narrow band gap material positioned on the surface of the substrate adjacent the body and at least a portion of the source, the layer of narrow band gap material having a narrower band gap than the band gap of the substrate.