US 2003/0070118 A1 · Semiconductor integrated circuit with built-in test function

Abstract

An execution time of a built-in test utilizing a decoder can be shortened by setting in parallel the codes of test pattern generator during execution of a self-test in order to eliminate an event that a test execution time increases due to increase of the time required for setting the test codes when the number of test codes increases. Namely a semiconductor integrated circuit with a built-in test (BIT) function is provided with a test code backup register for storing the codes of a test pattern generator, a test clock generator and a BIT controller to realize a function to set the codes required for execution of the next self-test in parallel to execution of the self-test and a function to immediately shift to the next self-test upon completion of the first self-test execution. A tester periodically observes a self-test end signal BEND during execution of a self-test and immediately applies the next code to the semiconductor integrated circuit when it observes a signal indicating the end of the self-test. Thereby, the test execution time can be reduced in the built-in test utilizing the decoder because the time required for setting of codes for each unit self-test can be reduced almost to zero.

Claims20

Dependent claims

A semiconductor integrated circuit with built-in test function comprising:

a test-code register for storing test-codes of a plurality of unit self-tests of which operations are regulated with a test-code given from an external circuit;
a first clock signal used for setting said test-code to said test-code register;
a second clock signal used for operations of said unit self-tests;
an end signal indicating whether a unit self-test is completed or not;
and
a built-in test controller for inputting said first and second clock signals to generate a signal required for control of the circuit under test and said end signal,
wherein said built-in test controller automatically stops, when the unit self-test is completed, that said second clock signal is supplied to the circuit under test, and sets, when the unit self-test is completed, a signal value indicating the end of unit self-test to said end signal.

4 more elements

An automatic test code generation method in a semiconductor integrated circuit with a built-in test function, comprising the steps of;

adding the built-in test function to the circuit information designed for performing self-test of the circuit under test provided in said semiconductor integrated circuit;
and
after said step of adding, producing a test code based on the circuit information with addition of the built-in test function and parameters for test-code generation.

Dependencies are inferred from the claim text.

Semiconductor integrated circuit with built-in test function

Life of this patent

Semiconductor integrated circuit with built-in test function

Life of this patent

Abstract

Claims20