Parallel and point-to-point data bus architecture

Abstract

A parallel, point-to-point bus architecture for interconnecting two or more electronic components for data communication. The bus architecture includes a non-blocking crosspoint switch having a tap for interconnection to each component, a clock terminal for receiving a common clock signal and an interface for connecting each component to a tap of the crosspoint switch. Each interface includes parallel data terminals for coupling data signals between the crosspoint switch tap and the component, a clock terminal for coupling the common clock signal between the crosspoint switch tap and the component and a clock-to-data alignment system. The clock-to-data alignment system aligns the data signals coupled between the crosspoint switch tap and the component to the common clock signal. Simultaneous data communications at very high speeds can be achieved through use of the bus.

Dependencies are inferred from the claim text.