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US 2003/0070031 A1Published application
Local bus polling support buffer
AssigneeIntel Corporation
InventorsJohn S. Howard, Brad Hosler
Life of this patent
Estimating the term…
Abstract
A method and apparatus for allowing memory, cache and/or a processor to remain powered down while repetitive transactions are carried out on an I/O bus and actions are taken in response to feedback received from I/O devices coupled to the I/O bus.
Claims30
A computer system, comprising:
- a memory to maintain a first set of data;
- a processor coupled to the memory such that the processor has access to the first set of data;
- an I/O bus;
- and
- an I/O controller that is coupled to the memory such that the I/O controller also has access to the first set of data, coupled to the I/O bus, and further coupled to a buffer to maintain a second set of data that is comprised of a copy of at least a portion of the first set of data.
2 more elements
A method, comprising:
- copying at least a portion of a first set of data maintained in a memory and storing the copy as a second set of data in a local buffer;
- powering down the memory;
- performing at least one instance of a repetitive transaction on an I/O bus;
- receiving a feedback from an I/O device coupled to the I/O bus in response to the at least one instance of a repetitive transaction;
- and
- using the second set of data in the local buffer to take an action in response to the feedback without making an access to the memory, allowing the memory to be powered down.
3 more elements
A method, comprising:
- copying at least a portion of a first set of data maintained in a memory and storing the copy as a second set of data in a local buffer;
- powering down the memory;
- performing at least one instance of a repetitive transaction on an I/O bus;
- receiving a feedback from an I/O device coupled to the I/O bus in response to the at least one instance of a repetitive transaction;
- using the second set of data in the local buffer to take an action in response to the feedback;
- and
- waiting to make an access to the memory until another event unrelated to the feedback from the I/O device causes the memory to be powered up.
4 more elements
An apparatus, comprising:
- a first interface to an I/O bus;
- a second interface to a memory to maintain a first set of data;
- a local buffer to maintain a second set of data comprised of a copy of at least a portion of the first set of data;
- and
- controlling circuitry to perform transactions on the I/O bus, the controlling circuitry being coupled to the local buffer and the first and second interfaces.
2 more elements
A computer-readable medium containing a sequence of instructions, which when executed cause an I/O controller to:
- copy at least a portion of a first set of data maintained in a memory and store the copy as a second set of data in a local buffer;
- perform at least one instance of a repetitive transaction on an I/O bus;
- receive a feedback from an I/O device coupled to the I/O bus in response to the at least one instance of a repetitive transaction;
- and
- use the second set of data in the local buffer to take an action in response to the feedback without making an access to the memory, allowing the memory to be powered down.
2 more elements
A computer-readable medium containing a sequence of instructions, which when executed cause an I/O controller to:
- copy at least a portion of a first set of data maintained in a memory and store the copy as a second set of data in a local buffer;
- perform at least one instance of a repetitive transaction on an I/O bus;
- receive a feedback from an I/O device coupled to the I/O bus in response to the at least one instance of a repetitive transaction;
- use the second set of data in the local buffer to take an action in response to the feedback;
- and
- wait to make an access to the memory until another event unrelated to the feedback from the I/O device causes the memory to be powered up.
3 more elements
Dependencies are inferred from the claim text.