Memory device and computer system including circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages

A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

• a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode to adjust the value of the bias voltage as a function of a magnitude of the supply voltage;
• a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage;
• and
• a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

• a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode to output the supply voltage as the bias voltage;
• a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage;
• and
• a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

A refresh controller for controlling a refresh rate of dynamic data in an integrated circuit, the refresh controller comprising:

• a variable bias voltage generator adapted to receive a supply voltage and operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a low-power mode responsive to a bias voltage adjustment command that is generated external to the integrated circuit, the variable bias voltage generator operable in response to the command to adjust the value of the bias voltage as a function of a magnitude of the supply voltage;
• a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage;
• and
• a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

A refresh controller for controlling a refresh rate of dynamic data, the refresh controller comprising:

• a variable bias voltage generator adapted to receive a supply voltage, the variable bias voltage generator operable in a normal mode to generate a bias voltage having a substantially constant value, and operable in a first low-power mode to adjust the value of the bias voltage as a function of a magnitude of the supply voltage and operable in a second low-power mode to output the supply voltage as the bias voltage;
• a self-refresh oscillator coupled to the variable bias voltage generator to receive the bias voltage signal, the self-refresh oscillator developing a refresh clock signal having a frequency that is a function of the bias voltage;
• and
• a refresh control circuit coupled to the self-refresh oscillator to receive the refresh clock signal, the refresh control circuit operable in response to the refresh clock signal to develop refresh signals that control the refresh rate of the dynamic data as a function of the frequency of the refresh clock signal.

A memory device, comprising:

• an address decoder coupled to an address bus;
• a read/write circuit coupled to a data bus;
• a control circuit coupled to a control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array storing dynamic data;
• and
• a refresh controller coupled to the memory-cell array, control circuit and address decoder for controlling a refresh rate of the dynamic data, the refresh controller being adapted to receive a supply voltage and including a refresh oscillator that generates a refresh clock signal having a frequency that is a function of a bias voltage, the refresh circuit operable in a normal mode when the supply voltage is greater than a minimum value to apply a substantially constant bias voltage to the refresh oscillator and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a first refresh rate having a value determined by the frequency of the refresh clock signal, and the refresh controller operable in a low-power mode when the supply voltage is less than or equal to the minimum value to vary the bias voltage as a function of the supply voltage and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a second refresh rate having a variable value that is a function of the frequency of the refresh clock signal.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device including,
• an address decoder coupled to an address bus;
• a read/write circuit coupled to a data bus;
• a control circuit coupled to a control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit, the memory-cell array storing dynamic data;
• and
• a refresh controller coupled to the memory-cell array, control circuit, and address decoder for controlling a refresh rate of the dynamic data, the refresh controller being adapted to receive a supply voltage and including a refresh oscillator that generates a refresh clock signal having a frequency that is a function of a bias voltage, the refresh circuit operable in a normal mode when the supply voltage is greater than a minimum value to apply a substantially constant bias voltage to the refresh oscillator and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a first refresh rate having a value determined by the frequency of the refresh clock signal, and the refresh controller operable in a low-power mode when the supply voltage is less than or equal to the minimum value to vary the bias voltage as a function of the supply voltage and to generate refresh signals in response to the corresponding refresh clock signal, the refresh signals defining a second refresh rate having a variable value that is a function of the frequency of the refresh clock signal.