Faster method of erasing flash memory
AssigneeMicron Technology, Inc.
InventorCorley B. Wooldridge
Life of this patent
Estimating the term…
Abstract
An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory cells into logic 1 bits before any pre-programming operation is performed.
Claims45
A method of operating a flash memory device, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- and
- pre-programming the memory cells only if a leakage occurs after the memory cells are erased.
A method of operating a flash memory device, the method comprising:
- converting contents of a plurality of memory cells into first logic bits;
- and
- converting the contents of the memory cells into second logic bits only if a leakage occurs after the memory cells are converted into the first logic bits.
A method of operating a flash memory device, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- soft-programming the memory cells if a leakage occurs and a number of memory cells having leakage stays below a low limit;
- and
- pre-programming the memory cells if a leakage occurs and the number of memory cells having leakage exceeds the low limit and stays below a high limit.
A method of operating a flash memory device, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- verifying that all of the memory cells are erased;
- checking for a leakage among the memory cells;
- soft-programming the memory cells if a leakage occurs and a number of memory cells having leakage stays below a low limit;
- and
- pre-programming the memory cells if a leakage occurs and the number of memory cells having leakage exceeds the low limit and stays below a high limit.
A method of operating a flash memory device, the method comprising:
- (a) applying an erase pulse to erase a plurality of memory cells;
- (b) verifying that all of the memory cells are erased;
- (c) checking for a leakage among the memory cells;
- (d) if a leakage occurs and a number of memory cells having leakage is less than a first predetermined quantity, then:
- soft-programming the memory cells having leakage;
- and
- continuing the method from element (b);
- and
- (e) if a leakage occurs and the number of memory cells having leakage is greater than the first predetermined quantity and less than a second predetermined quantity, then:
- pre-programming the memory cells;
- and
- continuing the method from element (a).
A flash memory device comprising:
- a plurality of memory cells;
- and
- a controller to perform a method of erasing data in the memory cells, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- and
- pre-programming the memory cells only if a leakage occurs after the memory cells are erased.
A flash memory device comprising:
- a plurality of memory cells;
- a controller to perform a method of erasing data in the memory cells, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- soft-programming the memory cells if a leakage occurs and a number of memory cells having leakage stays below a low limit;
- and
- pre-programming the memory cells if a leakage occurs and the number of memory cells having leakage exceeds the low limit and stays below a high limit.
A system comprising:
- processor;
- and
- a flash memory device connected to the processor, the memory device including a circuit to perform a method, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- and
- pre-programming the memory cells only if a leakage occurs after the memory cells are erased.
A computer-readable medium having instructions stored therein to cause a flash memory device to perform a method of erasing memory cells in the flash memory device, the method comprising:
- applying an erase pulse to erase a plurality of memory cells;
- and
- pre-programming the memory cells only if a leakage occurs after the memory cells are erased.
Dependencies are inferred from the claim text.