EEPROM flash memory erasable line by line

A method of reading, programming and erasing a memory comprising:

• a matrix (MEM) of cells connected to each other by means of row lines and column lines,
• row decoder circuits (DEC) comprising logic decoder units (DECx-z),
• voltage level conversion units (LSHx-z) and interface logic stages (ILOG) between the level conversion units (LSHx-z) and the row lines of the matrix,
• each interface stage comprising elementary row driving stages, each of which has inputs connected to corresponding outputs of the level conversion units (LSHx-z), an output connected to a row line (WL) and a first (SUPPLY_P) and a second (SUPPLY_N) supply voltage terminal and comprises a first branch comprising a first MOS transistor (P01) of a first type, connected with its source drain-path between the output (WL) and the first (SUPPLY_P) supply terminal and a second branch comprising a second MOS transistor (N01) of second type, connected with its source-drain path between the output (WL) and the second (SUPPLY_N) supply terminal, the gate terminals of the first and the second MOS transistor being two inputs of the elementary row driving stage,
• wherein the polarizations of the elementary row driving stages during the phases or reading and programming a cell of a row are chosen in such a manner that the first and the second branch of the elementary row driving stage function, respectively, as a pull-up branch and a pull-down branch, and
• wherein the polarizations of the elementary row driving stages during the phase of erasing a cell of a row are chosen in such a manner that the first and the second branch of the elementary row driving stage function, respectively, as a pull-down branch and a pull-up branch.

An EEPROM memory array word line control circuit, comprising, for each of a plurality of word lines in the memory array:

• a first pull circuit connected between each word line of the memory and a first voltage supply node, the first pull circuit including a first transistor of a first conductivity type;
• a second pull circuit connected between each word line of the memory and a second voltage supply node, the second pull circuit including a second transistor of a second conductivity type;
• wherein reading/programming of the certain word line is effectuated by biasing the first and second transistors high and relatively low, respectively, and configuring the first pull circuit for the certain word line as a pull-up and the second pull circuit for other word lines as a pull-down;
• and
• wherein erasure of memory cells associated with only the certain word line is effectuated by biasing the first and second transistors to ground and configuring the first pull circuit as a pull-down for the certain word line and the second pull circuit for other word lines as a pull-up.

A method for operating an EEPROM memory array, wherein each of a plurality of word lines includes a first pull branch and second pull branch connected to the word line, comprising the steps of:

• for reading/programming:
• activating the first pull branch for only a certain one of the word lines as a pull-up and activating the second pull branches for the other word lines as pull-downs;
• and
• for erasure:
• activating the first pull branch for only the certain one of the word lines as a pull-down and activating the second pull branches for the other word lines as pull-ups.

An EEPROM memory array word line control circuit, comprising, for each of a plurality of word lines in the memory array:

• a first pull circuit connected to a word line;
• and
• a second pull circuit connected to the word line;
• wherein reading/programming of memory cells associated with a certain word line is effectuated by configuring the first pull circuit for the certain word line as a pull-up and the second pull circuit for other word lines as a pull-down;
• and
• wherein erasure of memory cells associated with only the certain word line is effectuated by configuring the first pull circuit as a pull-down for the certain word line and the second pull circuit for other word lines as a pull-up.