Dual-phase delay-locked loop circuit and method

A delay-locked loop, comprising:

• a clock multiplier adapted to receive an input clock signal and operable to generate a multiplied clock signal responsive to the input clock signal, the multiplied clock signal having a frequency that is a multiple of the frequency of the input clock signal;
• a variable delay circuit coupled to the clock multiplier circuit and operable to generate a delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal;
• and
• a feedback delay circuit coupled to the variable delay circuit, the feedback delay circuit generating a feedback clock signal responsive to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal;
• a phase detector coupled to the clock multiplier to receive the multiplied clock signal and coupled to the variable delay circuit, the phase detector generating the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal.

A delay-locked loop, comprising:

• a variable delay circuit adapted to receive an input clock signal and operable to generate a delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit operable to control the value of the delay responsive to a delay control signal;
• and
• a feedback delay circuit coupled to the variable delay circuit, the feedback delay circuit generating a feedback clock signal responsive to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal;
• a rising-edge phase detector adapted to receive the input clock signal and coupled to the variable delay circuit to receive the delayed clock signal, the rising-edge phase detector generating the delay control signal in response to the relative phases of rising-edges of the delayed clock signal and the input clock signal;
• and
• a falling-edge phase detector adapted to receive the input clock signal and coupled to the variable delay circuit to receive the delayed clock signal, the falling-edge phase detector generating the delay control signal in response to the relative phases of falling-edges of the delayed clock signal and the input clock signal.

A delay-locked loop, comprising:

• an input buffer adapted to receive an input clock signal and operable to generate a buffered clock signal responsive to the input clock signal;
• a clock multiplier coupled to the input buffer and operable to generate a multiplied clock signal responsive to the buffered clock signal, the multiplied clock signal having a frequency that is a multiple of the frequency of the buffered clock signal;
• a variable delay line coupled to the clock multiplier and operable to generate a delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• and
• a feedback delay line coupled to the variable delay line, the feedback delay line generating a feedback clock signal responsive to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal;
• a phase detector coupled to the clock multiplier to receive the multiplied clock signal and coupled to the feedback delay line to receive the feedback clock signal, the phase detector generating the delay control signal in response to the relative phases of the buffered and feedback clock signals;
• a clock divider coupled to the variable delay line to receive the delayed clock signal, and operable to generate a divided clock signal responsive to the delayed clock signal, the divided clock signal having a frequency that is a sub-multiple of a frequency of the delayed clock signal;
• a phase detection and correction circuit coupled to the clock divider to receive the divided clock signal and adapted to receive the input clock signal, the circuit operable to detect a phase difference between the two clock signals, and operable in a first mode when detected phase equals approximately 180 degrees to generate an output clock signal that is inverted relative to the divided clock signal, and operable in a second mode to provide the divided clock signal as the output clock signal;
• and
• an output buffer coupled to the phase correction and detection circuit and operable to generate a synchronized clock signal in response to the output clock signal.

A delay-locked loop, comprising

• an input buffer circuit adapted to receive an input clock signal and operable to generate a buffered clock in response to the input clock signal;
• a variable delay line coupled to the input buffer and operable to generate a delayed clock signal responsive to the buffered clock signal, the delayed clock signal having a delay relative to the buffered clock signal and the variable delay line operable to control the value of the delay responsive to a delay control signal;
• a feedback delay line coupled to the variable delay line, the feedback delay line generating a feedback clock signal responsive to the delayed clock signal, the feedback clock signal having a model delay relative to the delayed clock signal;
• a rising-edge phase detector coupled to the input buffer to receive the buffered clock signal and coupled to the variable delay line to receive the delayed clock signal, the rising-edge phase detector generating the delay control signal in response to the relative phases of rising-edges of the delayed clock signal and the buffered clock signal;
• a falling-edge phase detector adapted to receive the input clock signal and coupled to the variable delay line to receive the delayed clock signal, the falling-edge phase detector generating the delay control signal in response to the relative phases of falling-edges of the delayed clock signal and the buffered clock signal.
• an output buffer coupled to the variable delay line to receive the delayed clock signal, the output buffer circuit generating a synchronized clock signal in response to the delayed clock signal.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising,
• a clock multiplier that generates a multiplied clock signal responsive to the input clock signal, the multiplied clock signal having a frequency that is a multiple of a frequency of the input clock signal;
• a variable delay circuit coupled to the clock multiplier and operable to generate the delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal;
• and
• a comparison circuit coupled to the clock multiplier and to the variable delay circuit, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising,
• a variable delay circuit coupled to the input clock signal and operable to generate the delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal;
• and
• a comparison circuit coupled to the variable delay circuit, the comparison circuit operable to generate the delay control signal in response to the relative phases of the rising-edge transitions of the delayed and input clock signals and in response to the relative phases of the falling-edge transitions of the delayed and input clock signals.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising,
• a clock multiplier that generates a multiplied clock signal responsive to the input clock signal, the multiplied clock signal having a frequency that is a multiple of a frequency of the input clock signal;
• a variable delay circuit coupled to the clock multiplier and operable to generate the delayed clock signal responsive to the multiplied clock signal, the delayed clock signal having a delay relative to the multiplied clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal;
• and
• a comparison circuit coupled to the clock multiplier and to the variable delay circuit, the comparison circuit operable to generate the delay control signal in response to the relative phases of the delayed clock signal and the multiplied clock signal.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, the memory device comprising,
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• a delay-locked loop coupled to at least the control circuit and adapted to receive an input clock signal, the delay-locked loop operable to generate a delayed clock signal and the control circuit generating control signals in response to the delayed clock signal, the delay-locked loop comprising,
• a variable delay circuit coupled to the input clock signal and operable to generate the delayed clock signal responsive to the input clock signal, the delayed clock signal having a delay relative to the input clock signal and the variable delay circuit controlling the value of the delay responsive to a delay control signal;
• and
• a comparison circuit coupled to the variable delay circuit, the comparison circuit operable to generate the delay control signal in response to the relative phases of the rising-edge transitions of the delayed and input clock signals and in response to the relative phases of the falling-edge transitions of the delayed and input clock signals.

A method for generating a delayed clock signal having a delay relative to an applied clock signal, the method comprising:

• generating a multiplied clock signal having a frequency that is a multiple of the applied clock signal;
• generating the delayed clock signal in response to the multiplied clock signal;
• delaying the delayed clock signal relative to the multiplied clock signal;
• detecting a phase difference between the multiplied clock signal and the delayed clock signal;
• and
• adjusting the delay of the delayed clock signal responsive to the detected phase difference.

A method for generating a delayed clock signal having a delay relative to an applied clock signal, the method comprising:

• generating the delayed clock signal in response to the applied clock signal;
• delaying the delayed clock signal relative to the applied clock signal;
• detecting a phase difference between rising edges of the delayed clock signal and rising-edges of the applied clock signal;
• detecting a phase difference between falling edges of the delayed clock signal and falling edges of the applied clock signal;
• and
• adjusting the delay of the delayed clock signal responsive to the detected phase differences.