Configurable logic block with and gate for efficient multiplication in FPGAS

A field programmable gate array comprising:

• a plurality of CLBs each having a plurality of lookup table function generators, each such lookup table function generator having a plurality of N input lines for selecting one of 2N memory cells;
• a carry chain having a carry input and a carry output and a plurality of serially arrayed carry multiplexers, each associated with a carry chain input multiplexer one input to which is provided by an AND gate, at least one respective such carry multiplexer being controlled by an output from a corresponding lookup table function generator, each carry multiplexer having at least two inputs, one such input being provided by a previous carry multiplexer in said carry chain and the other such input being provided by an output of said carry chain input multiplexer, said carry chain input multiplexer receiving one input from said AND gate.

In an FPGA, a CLB receiving input signals and providing output signals, said CLB comprising:

• a two-input AND gate receiving as input signals two of said CLB input signals and selectively providing one of said CLB output signals.