Generation of route rules

A system that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, said routing rule generation tool further comprises:
• a noise sensitivity/gate characterization tool that characterizes a suitable number of representative logic gates for noise sensitivity and determines the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain;
• a rule generator tool that generates route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate;
• and
• said route rule database that stores information regarding the gate types and gate sensitivities of said representative logic gates;
• a block build tool that interconnects said logic gates with routes according to the route rules generated by said routing rule generation tool, said block build tool further comprises:
• a gate sizing tool that sizes said logic gates using estimates for interconnect capacitance and resistance;
• a gate analysis tool that compares the noise sensitivity for various receiving logic gates;
• a route rule selecting tool that selects a route rule according to the most noise sensitive logic gate receiving the route;
• and
• a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A method of building a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• providing a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, said routing rule generation tool further comprises:
• a noise sensitivity/gate characterization tool that characterizes a suitable number of representative logic gates for noise sensitivity and determines the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain;
• a rule generator tool that generates route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate;
• and
• said route rule database that stores information regarding the gate types and gate sensitivities of said representative logic gates;
• providing a block build tool that interconnects said logic gates with routes according to the route rules generated by said routing rule generation tool, said block build tool further comprises:
• a gate sizing tool that sizes said logic gates using estimates for interconnect capacitance and resistance;
• a gate analysis tool that compares the noise sensitivity for various receiving logic gates;
• a route rule selecting tool that selects a route rule according to the most noise sensitive logic gate receiving the route;
• and
• a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A method of using a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• creating a route rule database for a given semiconductor fabrication technology and circuit family of logic gates with a routing rule generation tool, said routing rule generation tool further comprises:
• characterizing a suitable number of representative logic gates for noise sensitivity and determining the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain with a noise sensitivity/gate characterization tool;
• generating route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate with a rule generator tool;
• and
• storing information regarding the gate types and gate sensitivities of said representative logic gates in said route rule database;
• interconnecting said logic gates with routes according to the route rules generated by said routing rule generation tool with a block build tool, said block build tool further comprises:
• sizing said logic gates using estimates for interconnect capacitance and resistance with a gate sizing tool;
• comparing the noise sensitivity for various receiving logic gates with a gate analysis tool;
• selecting a route rule according to the most noise sensitive logic gate receiving the route with a route rule selecting tool;
• and
• using a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A program storage device readable by a computer that tangibly embodies a program of instructions executable by the computer to perform a method of using a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• creating a route rule database for a given semiconductor fabrication technology and circuit family of logic gates with a routing rule generation tool, said routing rule generation tool further comprises:
• characterizing a suitable number of representative logic gates for noise sensitivity and determining the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain with a noise sensitivity/gate characterization tool;
• generating route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate with a rule generator tool;
• and
• storing information regarding the gate types and gate sensitivities of said representative logic gates in said route rule database;
• interconnecting said logic gates with routes according to the route rules generated by said routing rule generation tool with a block build tool, said block build tool further comprises:
• sizing said logic gates using estimates for interconnect capacitance and resistance with a gate sizing tool;
• comparing the noise sensitivity for various receiving logic gates with a gate analysis tool;
• selecting a route rule according to the most noise sensitive logic gate receiving the route with a route rule selecting tool;
• and
• using a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, said routing rule generation tool further comprises:
• a noise sensitivity/gate characterization tool that characterizes a suitable number of representative logic gates for noise sensitivity and determines the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain;
• a rule generator tool that generates route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate, said rule generator tool uses an optimizing SPICE simulation for each sensing gate type, driving gate strength, sensing gate size, connecting route type, and charge sharing assumption to determine the required route length;
• and
• said route rule database that stores information regarding the gate types and gate sensitivities of said representative logic gates;
• a block build tool that interconnects said logic gates with routes according to the route rules generated by said routing rule generation tool, said block build tool interconnects said logic gates with routes so that said logic gates are immune to malfunction due to noise effects while retaining maximum circuit performance and minimizing the redesign of the semiconductor device due to discovery of noise problems, said block build tool further comprises:
• a gate sizing tool that sizes said individual gates using estimates for interconnect capacitance and resistance;
• a gate analysis tool that compares the noise sensitivity for various receiving logic gates;
• a route rule selecting tool that selects a route rule according to the most noise sensitive logic gate receiving the route;
• and
• a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A system that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, said routing rule generation tool further comprises:
• a noise sensitivity/gate characterization tool that characterizes a suitable number of representative logic gates for noise sensitivity and determines the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain;
• a rule generator tool that generates route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate, said rule generator tool uses an optimizing SPICE simulation for each sensing gate type, driving gate strength, sensing gate size, connecting route type, and charge sharing assumption to determine the required route length;
• and
• said route rule database that stores information regarding the gate types and gate sensitivities of said representative logic gates;
• a block build tool that interconnects said logic gates with routes according to the route rules generated by said routing rule generation tool, said block build tool interconnects said logic gates with routes so that said logic gates are immune to malfunction due to noise effects while retaining maximum circuit performance and minimizing the redesign of the semiconductor device due to discovery of noise problems, said block build tool further comprises:
• a gate sizing tool that sizes said logic gates using estimates for interconnect capacitance and resistance;
• a gate analysis tool that compares the noise sensitivity for various receiving logic gates;
• a route rule selecting tool that selects a route rule according to the most noise sensitive logic gate receiving the route;
• and
• a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A method of building a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• providing a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, said routing rule generation tool further comprises:
• a noise sensitivity/gate characterization tool that characterizes a suitable number of representative logic gates for noise sensitivity and determines the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain;
• a rule generator tool that generates route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate, said rule generator tool uses an optimizing SPICE simulation for each sensing gate type, driving gate strength, sensing gate size, connecting route type, and charge sharing assumption to determine the required route length;
• and
• said route rule database that stores information regarding the gate types and gate sensitivities of said representative logic gates;
• providing a block build tool that interconnects said logic gates with routes according to the route rules generated by said routing rule generation tool, said block build tool interconnects said logic gates with routes so that said logic gates are immune to malfunction due to noise effects while retaining maximum circuit performance and minimizing the redesign of the semiconductor device due to discovery of noise problems, said block build tool further comprises:
• a gate sizing tool that sizes said logic gates using estimates for interconnect capacitance and resistance;
• a gate analysis tool that compares the noise sensitivity for various receiving logic gates;
• a route rule selecting tool that selects a route rule according to the most noise sensitive logic gate receiving the route;
• and
• a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A method of using a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• creating a route rule database for a given semiconductor fabrication technology and circuit family of logic gates with a routing rule generation tool, said routing rule generation tool further comprises:
• characterizing a suitable number of representative logic gates for noise sensitivity and determining the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain with a noise sensitivity/gate characterization tool;
• generating route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate with a rule generator tool, said rule generator tool uses an optimizing SPICE simulation for each sensing gate type, driving gate strength, sensing gate size, connecting route type, and charge sharing assumption to determine the required route length;
• and
• storing information regarding the gate types and gate sensitivities of said representative logic gates in said route rule database;
• interconnecting said logic gates with routes according to the route rules generated by said routing rule generation tool with a block build tool, said block build tool interconnects said logic gates with routes so that said logic gates are immune to malfunction due to noise effects while retaining maximum circuit performance and minimizing the redesign of the semiconductor device due to discovery of noise problems, said block build tool further comprises:
• sizing said logic gates using estimates for interconnect capacitance and resistance with a gate sizing tool;
• comparing the noise sensitivity for various receiving logic gates with a gate analysis tool;
• selecting a route rule according to the most noise sensitive logic gate receiving the route with a route rule selecting tool;
• and
• using a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.

A program storage device readable by a computer that tangibly embodies a program of instructions executable by the computer to perform a method of using a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device, comprising:

• creating a route rule database for a given semiconductor fabrication technology and circuit family of logic gates with a routing rule generation tool, said routing rule generation tool further comprises:
• characterizing a suitable number of representative logic gates for noise sensitivity and determining the conditions under which an individual logic gate being characterized amplifies input noise with a certain gain with a noise sensitivity/gate characterization tool;
• generating route rules that are derived using said representative logic gates using assumptions about internal charge sharing and supply voltage differences of said individual logic gate with a rule generator tool, said rule generator tool uses an optimizing SPICE simulation for each sensing gate type, driving gate strength, sensing gate size, connecting route type, and charge sharing assumption to determine the required route length;
• and
• storing information regarding the gate types and gate sensitivities of said representative logic gates in said route rule database;
• interconnecting said logic gates with routes according to the route rules generated by said routing rule generation tool with a block build tool, said block build tool interconnects said logic gates with routes so that said logic gates are immune to malfunction due to noise effects while retaining maximum circuit performance and minimizing the redesign of the semiconductor device due to discovery of noise problems, said block build tool further comprises:
• sizing said logic gates using estimates for interconnect capacitance and resistance with a gate sizing tool;
• comparing the noise sensitivity for various receiving logic gates with a gate analysis tool;
• selecting a route rule according to the most noise sensitive logic gate receiving the route with a route rule selecting tool;
• and
• using a route assigning tool that performs the application of route rules to said logic gates in the semiconductor design.