Enhanced and adaptive error detection in digital communications

A method of receiving a codeword that comprises one or more information bits, a first set of error detection check bits and a second set of error detection check bits, the method comprising:

• using the first set of error detection check bits to make a first determination whether the one or more information bits are error-free;
• using the second set of error detection check bits to make a second determination whether the one or more information bits and the first set of error detection check bits are error-free;
• and
• accepting the one or more information bits only if the first determination indicates that the one or more information bits are error-free and the second determination indicates that the one or more information bits and the first set of error detection check bits are error-free.

A method of receiving a codeword that comprises one or more information bits and a plurality of sets of error detection check bits, wherein each of the sets of error detection check bits is associated with a corresponding portion of the codeword, the method comprising:

• determining how many error detection checks should be performed;
• until the determined number of error detection checks are performed, repeatedly using a different one of the sets of error detection check bits to determine whether the corresponding portion of the received codeword contains an error;
• and
• disregarding all remaining unused different ones of the sets of error detection check bits.

An apparatus for generating a codeword for transmission in a communications system, the apparatus comprising:

• a first error detection code generator that generates a first set of error detection check bits from one or more information bits;
• a second error detection code generator that generates a second set of error detection check bits from the one or more information bits and the first set of error detection check bits;
• and
• logic that concatenates the one or more information bits, the first set of error detection check bits and the second set of error detection check bits.

An apparatus for receiving a codeword that comprises one or more information bits, a first set of error detection check bits and a second set of error detection check bits, the apparatus comprising:

• logic that uses the first set of error detection check bits to make a first determination whether the one or more information bits are error-free;
• logic that uses the second set of error detection check bits to make a second determination whether the one or more information bits and the first set of error detection check bits are error-free;
• and
• logic that accepts the one or more information bits only if the first determination indicates that the one or more information bits are error-free and the second determination indicates that the one or more information bits and the first set of error detection check bits are error-free.

An apparatus for receiving a codeword that comprises one or more information bits and a plurality of sets of error detection check bits, wherein each of the sets of error detection check bits is associated with a corresponding portion of the codeword, the apparatus comprising:

• logic that determines how many error detection checks should be performed;
• and
• error detection logic that operates until the determined number of error detection checks are performed, by repeatedly using a different one of the sets of error detection check bits to determine whether the corresponding portion of the received codeword contains an error,
• wherein the error detection logic disregards all remaining unused different ones of the sets of error detection check bits.