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US 2002/0178414 A1Published application
Synchronous flash memory with test code input
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals provided on the address input connections and not the data input/output connections. The test mode can be entered using either commands or a combination of commands and an electronic key.
Claims41
A non-volatile memory device comprising:
- address input connections to receive externally provided signals;
- and
- control circuitry coupled to the address input connections to place the non-volatile memory device in a test mode selected by the externally provided signals.
A flash memory device comprising:
- an array of non-volatile memory cells;
- control input connections to receive control signals;
- data connections for bi-directional data communication;
- address input connections to receive externally provided address and test mode code signals;
- and
- control circuitry coupled to the address input connections to place the non-volatile memory device in a test mode selected by the test mode code signals.
3 more elements
A memory system comprising:
- an external memory controller;
- and
- a flash memory device coupled to the external memory controller, the flash memory device comprises,
- an array of non-volatile memory cells,
- control input connections to receive control signals from the external memory controller,
- data connections for bidirectional data communication with the external memory controller,
- address input connections to receive externally provided address and test mode code signals from the external memory controller, and
- control circuitry coupled to the address input connections to place the non-volatile memory device in a test mode selected by the test mode code signals.
5 more elements
A method of testing a non-volatile memory device comprising:
- initiating a test operation of the non-volatile memory device;
- and
- selecting a test mode in response to a test code provided on address inputs.
A method of testing a non-volatile memory device comprising:
- checking a state of a test latch circuit;
- receiving test mode commands on address inputs;
- placing the non-volatile memory device in a test mode if the test latch circuit is in a first state, and prohibiting the test mode if the test latch circuit is in a second state;
- and
- selecting a test mode in response to a test code provided on the address inputs.
2 more elements
A method of operating a non-volatile memory device comprising:
- performing a first Load Command Register operation, wherein the first Load Command Register operation comprises receiving a test mode command on address input connections when a chip select input is active, a row access strobe input is active, a column access strobe input is active and a write enable input is inactive, wherein the test mode command initiates a test mode;
- and
- performing a second Load Command Register operation, wherein the second Load Command Register operation comprises receiving a test code command on address input connections when a chip select input is active, a row access strobe input is active, a column access strobe input is active and a write enable input is inactive, wherein the test code command instructs the memory device to perform a selected test operation.
A method of testing a non-volatile memory device comprising:
- checking a state of a non-volatile test latch circuit;
- receiving test mode commands on address inputs;
- placing the non-volatile memory device in a test mode if the test latch circuit is in a first state, and prohibiting the test mode if the test latch circuit is in a second state;
- placing the non-volatile memory device in the test mode if the test latch circuit is in the second state, and a high voltage signal is detected on a pre-determined address input;
- and
- selecting a test mode in response to a test code provided on the address inputs.
3 more elements
A method of testing a memory device having X selectable tests, the method comprises:
- initiating a test mode;
- and
- selecting one of the X selectable tests using a test code provided on address input connections.
A flash memory device comprising:
- an array of non-volatile memory cells;
- control input connections to receive control signals;
- X-data connections for bidirectional data communication;
- address input connections to receive externally provided address;
- and
- control circuitry to place the memory in a compressed data mode such that X-bits of data are communicated using X/Y data connections, and wherein the control circuitry is coupled to the address input connections to place the non-volatile memory device in a test mode selected by test mode code signals.
3 more elements
A method of testing a non-volatile memory device comprising:
- placing the non-volatile memory in a compressed data mode such that X-bits of data are communicated on X/Y data connections;
- checking a state of a test latch circuit;
- receiving test mode commands on address inputs;
- placing the non-volatile memory device in a test mode if the test latch circuit is in a first state, and prohibiting the test mode if the test latch circuit is in a second state;
- and
- selecting a test mode in response to a test code provided on the address inputs.
3 more elements
A method of testing a non-volatile memory device comprising:
- placing the non-volatile memory in a compressed data mode such that X-bits of data are communicated on X/Y data connections;
- checking a state of a non-volatile test latch circuit;
- receiving test mode commands on address inputs;
- placing the non-volatile memory device in a test mode if the test latch circuit is in a first state, and prohibiting the test mode if the test latch circuit is in a second state;
- placing the non-volatile memory device in the test mode if the test latch circuit is in the second state, and a high voltage signal is detected on a pre-determined address input;.and
- selecting a test mode in response to a test code provided on the address inputs.
3 more elements
Dependencies are inferred from the claim text.