Time data compression technique for high speed integrated circuit memory devices

A time data compression circuit comprising:

• a first sorting circuit for receiving an input data rate signal and providing corresponding first and second lower data rate signals at first and second outputs thereof;
• a second sorting circuit coupled to said first output of said first sorting circuit for providing third and fourth relatively lower data rate signals in response to said first lower data rate signal;
• a third sorting circuit coupled to said second output of said first sorting circuit for providing fifth and sixth relatively lower data rate signals in response to said second lower data rate signal;
• and
• a compare circuit coupled to receive said third, fourth, fifth and sixth relatively lower data rate signals from said second and third sorting circuits, said compare circuit producing a first output signal when said third, fourth, fifth and sixth relatively lower data rate signals are at a same logic level and a second output signal when said third, fourth, fifth and sixth relatively lower data rate signals are not all at said same logic level.

A method for time data compression comprising:

• receiving an input data rate signal;
• transforming said input data rate signal to first and second lower data rate signals;
• comparing said first and second lower data rate signals;
• outputting a first output signal when said first and second lower data rate signals are at a same logic level;
• and
• outputting a second output signal when said first and second lower data rate signals are at an opposite logic level.

A method for time data compression comprising:

• receiving an input data rate signal;
• firstly transforming said input data rate signal to first and second lower data rate signals;
• secondly transforming said first and second lower data rate signals to third, fourth, fifth and sixth relatively lower data rate signals;
• comparing said third, fourth fifth and sixth relatively lower data rate signals;
• outputting a first output signal when said third, fourth fifth and sixth relatively lower data rate signals are at a same logic level;
• and
• outputting a second output signal when said third, fourth fifth and sixth relatively lower data rate signals are not all at said same logic level.