Method and apparatus for calibrating a test system for an integrated semiconductor circuit
AssigneeInfineon Technologies AG
InventorHans-Christoph Ostendorf
Life of this patent
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Abstract
A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.
Claims10
A method for calibrating a test system for an integrated semiconductor circuit, comprising the steps of:
- generating a test signal in the form of a pattern of successive rising and falling edges by a pattern generator of a test system, said test signal including superposed sub-patterns formed via different internal paths of the pattern generator;
- providing an information signal for a measuring device of the test system by the pattern generator, said information signal identifying edges of at least one sub-pattern of the test signal with regard to their origin from one of internal paths;
- and
- calibrating for the internal path separately using said information signal.
A method according to one of the preceding claims, wherein said calibrating step includes the sub-step of assigning a respective internal path a signal delay device, which is set taking account of a measurement result of the measuring device for a respective internal signal path.
An apparatus for calibrating a test system for an integrated semiconductor circuit, comprising:
- a pattern generator of the test system operable to generate a test signal in a form of a pattern of successive rising and falling edges, said test signal including superposed sub-patterns formed via different internal paths of the pattern generator;
- and
- a provision device for providing an information signal which identifies edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths.
Dependencies are inferred from the claim text.