Method and apparatus for increasing the effectiveness of system debug and analysis

A method for analyzing system operations comprising:

• 1) combining first outputs from an event counter and second outputs from a cycle clock counter to form an M-bit address;
• 2) generating N-trace storage addresses by a decode of said M-bit address;
• 3) incrementing said cycle clock counter in response to a gated cycle clock, wherein said gated cycle clock is gated on by a run latch set to a first state;
• 4) incrementing said event counter in response to a first event signal;
• 5) storing states of trace signals at said N-storage locations in a writeable trace array as selected by said N-trace storage addresses in response to a write enable of said trace array;
• 6) storing a start code in said trace array in response to occurrences of a first event signal, said start code stored in one of said N-storage locations in place of states of said trace signals;
• 7) storing a trace event address in response to each occurrence of said first event signal, said trace event address corresponding to said trace storage address generated before said event counter is incremented;
• and
• 8) repeating steps 1) through 7) until stopped in response to a second event signal.

A method for analyzing system operations comprising:

• 1) generating N-trace storage addresses by incrementing a cycle clock counter in response to a gated cycle clock, wherein said gated cycle clock is gated on by a start signal;
• 2) storing states of trace signals at said N-storage locations in a writeable trace array as selected by said N-trace storage addresses in response to a write enable of said trace array;
• 3) storing a start code in said trace array in response to occurrences of a first event signal, said start code stored in one of said N-storage locations in place of states of said trace signals;
• 4) analyzing a sequence of received states of said trace signals for a first sequence;
• 5) storing a compression code in said trace array in response to said first sequence;
• 6) storing a time stamp code in said trace array in response to a repeated number of said first sequence;
• 7) stopping said gated cycle clock in response said first sequence;
• 8) starting said gated cycle clock in response to a second sequence of said received states of said trace signals;
• 9) repeating steps 1) through 8) until stopped in response to a second event signal, wherein states of said trace signals are stored compressed.

An apparatus for analyzing system operations comprising:

• a writeable trace array, said trace array having N-storage locations, each of said N-storage locations selected by corresponding N-trace storage addresses;
• a coupling circuit to couple trace signals to said writeable trace array;
• an M-bit cycle clock counter;
• a decode circuit for decoding said M-bit address to generate said N-trace storage addresses;
• an index circuit for generating selected of said N-trace storage addresses by incrementing said cycle clock counter in response to a gated cycle clock, wherein said gated cycle clock is gated on by a start signal;
• a storage circuit for storing states of said trace signals in said N-storage locations of said trace array in response to a write enable of said trace array;
• a start code circuit for storing a start code in one of said N-storage locations of said trace array in place of states of said trace signals in response to a first event signal;
• and
• a stop circuit for stopping said storing of states of said trace signals in response to a second event signal.

An apparatus for analyzing system operations comprising:

• a writeable trace array, said trace array having N-storage locations, each of said N-storage locations selected by corresponding N-trace storage addresses;
• a coupling circuit for coupling trace signals to said writeable trace array;
• an event counter;
• a cycle clock counter;
• a combining circuit for combining first outputs from said event counter and second outputs from said cycle clock counter to form an M-bit address;
• a decode circuit for generating said N-trace storage addresses from a decode of said M-bit address;
• a first index circuit for incrementing said cycle clock in response to a gate cycle clock, said gated cycle clock gated on by a run latch set to a first state;
• a second index circuit for incrementing said event counter in response to a first event signal;
• a storage circuit for storing states of said trace signals in said N-storage locations of said trace array in response to a write enable of said trace array;
• a start code circuit for storing a start code in said trace array in response to an occurrence of said first event signal;
• an event storage circuit for storing a trace event address in response to occurrences of said first event signal, said trace event address corresponding to said trace storage address generated before said event counter is incremented;
• and
• a stop circuit for stopping said storing of states of said trace signals in response to a second event signal.

An apparatus for analyzing system operations comprising:

• a writeable trace array, said trace array having N-storage locations, each of said N-storage locations selected by corresponding N-trace storage addresses;
• a coupling circuit operable to couple trace signals to said writeable trace array,
• an M-bit cycle clock counter;
• said M-bits of said M-bit cycle clock counter producing an M-bit address;
• a decode circuit for decoding said M-bit address to generate said N-trace storage addresses;
• an address circuit generating selected of said N-trace storage addresses by incrementing said cycle clock counter in response to a gated clock, said gated cycle clock gated on by a run latch set to a first state;
• a storage circuit for storing states of said trace signals in said N-storage locations of said trace array in response to a write enable of said trace array;
• a start code circuit for storing a start code in said trace array in response to a first event signal;
• a sequence circuit for determining a first sequence of received states of said trace signals;
• a compression code circuit for storing a compression code in said trace array in response to an occurrence of said first sequence;
• a time stamp code circuit for storing a time stamp code in said trace array in response to a repeated number of occurrences of said first sequence;
• a first stop circuit for stopping said gated cycle clock in response an occurrence of said first sequence;
• a start circuit for starting said gated cycle clock in response to an occurrence of a second sequence of said received states of said trace signals;
• and
• a stop circuit for stopping said storing of states of said trace signals in response to a second event signal.

A data processing system comprising:

• a central processing unit (CPU);
• random access memory (RAM);
• read only memory (ROM);
• and
• a bus system coupling said CPU to said ROM and said RAM, wherein said CPU further comprises:
• a very large scale integrated (VLSI) chip, said VLSI chip comprising a debugging system for debugging circuits within said chip said debugging system comprising;
• a writeable trace array, said trace array having N-storage locations, each of said N-storage locations selected by corresponding N-trace storage addresses;
• circuitry for coupling said trace signals to said writeable trace array;
• circuitry configured as an M-bit cycle clock counter;
• said M-bits of said M-bit cycle clock counter producing an M-bit address;
• circuitry for decoding said M-bit address to generate said N-trace storage addresses;
• circuitry for generating selected of said N-trace storage addresses by incrementing said cycle clock counter in response to a gated cycle clock, wherein said gated cycle clock is gated on by a run latch set to a first state;
• a storage circuit for storing states of said trace signals in said N-storage locations of said trace array in response to a write enable of said trace array;
• circuitry for writing a start code in said trace array in response to a first event signal;
• and
• a stop circuit for stopping said storing of states of said trace signals in response to a second event signal.