Lowering priority and elimination scheme for useless instructions
AssigneeIntel Corporation
InventorsGeorge Elias, Adi Yoaz, Ronny Ronen
Life of this patent
Estimating the term…
Abstract
A method of executing instructions in an instruction window including the following actions. Examining the first and second instructions to determine the sources and destinations of the first and second instructions. Setting a written on bit of the first instruction to written on if the destinations of the first and second instructions are the same. Setting a used bit of the first instruction to used if the source of the second instruction is the destination of the first instruction. Determining a priority of the first instruction from the written on and used bits.
Claims30
A method, comprising:
- examining a first instruction to determine a first destination that the first instruction will write on, the first instruction to be in an instruction window;
- examining a second instruction to determine a first source that the second instruction will use and a second destination that the second instruction will write on, the second instruction to enter the instruction window;
- setting a written on bit associated with the first instruction to a written on state if the first destination and the second destination will be the same operand;
- setting a used bit associated with the first instruction to a used state if the first destination and the first source will be the same operand;
- and, determining a priority of the first instruction from the written on and used bits.
A processor, comprising:
- an instruction window including a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit;
- a fetcher to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, the prior instruction and the subsequent instruction include a source and a destination.
A computer system, comprising:
- a processor including
- an instruction window having a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit;
- a memory;
- and,
- a fetcher to fetch instructions from the memory and to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, both the prior instruction and subsequent instruction include a source, a destination, the written on bit of the first instruction entry to be set to a written on state if the destination of the prior instruction and the subsequent instruction are the same operand, and the used bit of the first instruction entry to be set to a used state if the source of the subsequent instruction and the destination of the prior instruction are the same operands.
A circuit, comprising:
- a written on logic to determine a written on bit;
- a used logic to determine a used bit;
- and,
- a priority logic to determine a priority based on the written on and the used bits, the written on, used and priority logics to be associated with a first instruction entry of a plurality of instruction entries in an instruction window, the plurality of instruction entries to include a second instruction entry, the first instruction entry to be occupied by a prior instruction and the second instruction entry to be occupied by a subsequent instruction, the first and second instructions each include a source and a destination.
Dependencies are inferred from the claim text.