Method and system for creating secure address space using hardware memory router
AssigneeHewlett-Packard Development Company, L.P.
InventorsKenneth Mark Wilson, Paul Keltcher, Yoshio Turner
Life of this patent
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Abstract
A method and system providing dynamic allocation of memory through hardware is disclosed. An embodiment provides for a multi-processor system providing for a secure partitioned memory. The system comprises a processor(s), a hardware implemented memory router coupled to the processor(s), and memory coupled to the memory router. The memory router stores memory partition information, which describes the memory allocated to the processor(s). Furthermore, the memory router maps a memory access request from a processor to an address in the memory.
Claims23
A system having a partitioned memory, said system comprising:
- a processor;
- a hardware implemented memory router coupled to said processor;
- memory coupled to said memory router;
- said memory router configured to store memory partition information, said information describing the memory allocated to said processor;
- and
- said memory router operable to map a memory access request having an address from said processor to an address in said memory allocated to said processor.
A method of partitioning memory, said method comprising the steps of:
- a) a hardware implemented memory router receiving a request for memory access from one of a plurality of processors, said request specifying a first address;
- b) said hardware memory router determining the location in memory corresponding to said first address, said memory partitioned among said plurality of processors;
- and
- c) said hardware memory router routing said memory request to said memory, wherein said memory access is securely executed such that said one of said plurality of processors is only able to access memory which is allocated to it.
A hardware implemented memory router comprising:
- an input to receive an memory access request, said request specifying an address in a first processor's of a plurality of processors address space;
- a table for storing memory partition information, said information describing the memory allocated to each of said plurality of processors;
- and
- logic operable to translate said address in said processor address space to a corresponding address in said memory.
Dependencies are inferred from the claim text.