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US 2002/0178324 A1Published application
High performance cost optimized memory
AssigneeRambus Inc.
InventorsRichard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
Life of this patent
Estimating the term…
Abstract
A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.
Claims7
A memory device, comprising:
- a plurality of external connections for receiving row operation information, column operation information and data information, said row operation information including precharge commands and sense commands, said column operation information including read commands, write commands and mask data, said plurality of external connections including a first subset of external connections receiving sense, read and write commands, a second subset of external connections receiving precharge commands and mask data, and a third subset of external connections receiving data information;
- a memory core for storing said data information;
- and
- memory interface circuitry coupled between said plurality of external connections and said memory core, for operating on said memory core in accordance with said row operation information and said column operation information, said memory interface circuitry receiving precharge information on said second subset of external connections in association with a read command or an unmasked write command, said memory interface circuitry receiving mask data on said second subset of external connections in association with a masked write command.
1 more element
A memory device, comprising:
- a group of external connections;
- a memory core for storing data;
- and
- a memory interface circuit connected between said group of external connections and said memory core, said group of external connections providing control information in a given time to said memory device, wherein a portion of said control information is shared between precharge control information, write mask control information, or tri-state control information.
1 more element
A semiconductor device package, comprising:
- a semiconductor die with interface circuitry including a number of connection sites for coupling to external signals;
- and
- packaging material for housing said semiconductor die, said packaging material having a lead side with a number of leads, said lead side being adjacent to and spanning a greater distance than the side of said semiconductor die with said connection sites, the number of leads on said packaging material exceeding the number of said connection sites;
- wherein all said connection sites are connected to packaging material leads by a length of conductive metal, the length of conductive metal being a function of the position of the lead and associated connection site, wherein excess leads of said packaging material are coupled to a length of conductive metal at ground potential to provide shielding to said lengths of conductive metal connected to said connection sites.
1 more element
Dependencies are inferred from the claim text.