Semiconductor memory device having refresh circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMasaki Tsukude, Shinichi Kobayashi, Hirotoshi Sato
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Abstract
In a semiconductor memory device, a refresh circuit outputs a refresh command signal for executing refresh operation. The refresh circuit includes a command-signal activating circuit for activating the refresh command signal, and a determination circuit for determining whether the activated refresh command signal is to be output. The determination circuit determines that the activated refresh command signal is to be output when the semiconductor memory device is in a standby state. Thereby, the semiconductor memory device enables stable refresh operation to be executed.
Claims8
A semiconductor memory device having an operation state where a read operation and a write operation for data are executable and a standby state where said data is retained, comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- and
- a complete hidden refresh circuit for performing a refresh operation without being externally commanded for said data stored in said plurality of memory cells,
- wherein said complete hidden refresh circuit executes said refresh operation according to the condition of said semiconductor memory device.
Dependencies are inferred from the claim text.