Method and architecture for accessing hardware devices in computer system and the chipset thereof

An architecture for accessing a hardware device in a computer system comprising:

• a first bus;
• a second bus;
• a third bus;
• a first controller coupled between said first bus and second bus and having a master controller of said first bus and a slave controller of said third bus;
• a second controller coupled with said second bus for coordinating data transfers among a central processing unit, a main memory, a video graphic adapter controller and said first bus;
• and
• an input-output device having a master controller of said third bus;
• wherein said third bus is coupled between said input-output device and said first controller, said master controller of said third bus is configured to transmit a data signal defined by a protocol of said third bus to said slave controller of said third bus, in order to drive said master controller of said first bus to access said hardware device.

A method of accessing a hardware device which is coupled with a first bus through a two-wired serial interface, comprising the steps of:

• generating a clock signal, and transmitting a data signal defined by a protocol of said two-wired serial interface from a master controller of said two-wired serial interface through said two-wired serial interface with reference to said clock signal;
• receiving said clock signal and said data signal by a controller having a master controller of said first bus and a slave controller of said two-wired serial interface;
• and
• according to a command and a data byte in said data signal, driving said master controller of said first bus to access said hardware device according to a read/write cycle of said first bus.