Floating point multiplier for delimited operands
AssigneeSun Microsystems, Inc.
InventorGuy L. Steele JR.
Life of this patent
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Abstract
A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
Claims21
A method for providing a floating point product, comprising:
- multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages;
- and
- correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
A system for providing a floating point product comprising a multiplying circuit for multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages, wherein an error introduced by the subprecise operand is corrected by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
A computer-readable medium on which is stored a set of instructions for providing a floating point product, which when executed perform stages comprising:
- multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages;
- and
- correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.
Dependencies are inferred from the claim text.