Distributed logic analyzer for use in a hardware logic emulation system
OwnerStephen P. Sampleinventor
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Abstract
A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
Claims16
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being interconnected to each other by a plurality of interconnect chips, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising:
- at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design;
- at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design;
- and
- control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
A logic analyzer integrated in a hardware logic emulation system that emulates a logic design, the logic emulation system comprising a plurality of logic chips, the plurality of logic chips being programmably interconnected to each other, the logic design comprising combinational logic elements and sequential logic elements, the logic analyzer comprising:
- at least one scan chain programmed into each of said plurality of logic chips, said at least one scan chain comprised of a flip-flop, said at least one scan chain programmably connectable to outputs of a selected subset of the sequential logic elements of the logic design;
- at least one memory device, said at least one memory device in communication with said at least one scan chain and storing data from the sequential logic elements of the logic design;
- and
- control circuitry, said control circuitry in communication with said plurality of logic chips, said control circuitry generating logic analyzer clock signals and trigger signals, said logic analyzer clock signals clocking said at least one scan chain, said trigger signals being generated when a predetermined combination of signals occur in said plurality of logic chips.
Dependencies are inferred from the claim text.