Gate etch process for 12 inch wafers
OwnerVirinder Grewal, Thomas Morgensterninventors
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Abstract
A method for fabricating a stacked gate array on a semiconductor 12 inch wafer uses a reaction chamber with an upper inductive means and a lower capacitive means. For etching 12 inch wafers the etching parameters are adjusted to values optimised for etching an 8 inch wafer. In particular the power of the upper inductive means is set to a value between 50 and 600 Watts.
Claims18
A method for fabricating a stacked gate array on a semiconductor wafer with a diameter of more than 8 inch comprising the steps of:
- Providing a reaction chamber having an upper inductive means and a lower capacitive means;
- Adjusting power settings of said upper inductive means for obtaining a uniformity better than 10% in etching a wafer with a diameter of 8 inch at a rate of etching between 50 and 500 nm/min;
- Placing said wafer with a diameter of more 8 inch into said reaction chamber;
- and
- Plasma etching said wafer with a diameter of more than 8 inch to provide said stacked gate array.
A method for etching a semiconductor wafer with a diameter of 10 or more inch comprising the steps of:
- Providing a reaction chamber having an upper inductive means and a lower capacitive means;
- Adjusting power settings of said upper inductive means which are suited to etch a wafer with a diameter of 8 inch to obatin stacked gates of MOSFETs on said wafer of 8 inch;
- Placing said wafer with a diameter of 10 or more inch into said reaction chamber;
- and
- Plasma etching said wafer with a diameter of 10 or more inch to obtain stacked gates of MOSFETs.
A method for etching a semiconductor wafer with a diameter of 10 or more inch comprising the steps of:
- Providing a reaction chamber having an upper inductive means and a lower capacitive means;
- Adjusting power settings of said upper inductive means to between 50 and 600 Watts;
- Adjusting power settings of said lower capacitive means to less than 200 Watts;
- Providing a wafer having a layer of a metal silicide, a layer of polysilicon and a layer of a gate oxide;
- Placing said wafer into said reaction chamber;
- and
- Plasma etching said wafer relative to a mask thereby removing said layers of metal silicide and polysilicon where not protected by said mask and maintaining said layers of metal silicide and polysilicon and gate oxide where protected by said mask in order to obtain stacked transistor gates.
Dependencies are inferred from the claim text.