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AssigneeInternational Business Machines Corporation
InventorsJames W. Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
Estimating the term…
A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
A FET comprising:
An integrated circuit chip having a plurality of field effect transistors therein, said transistors having narrow channel thickness and different threshold voltages, said threshold voltages determined by combination and adjacent positioning of at least two different gate materials, wherein said gate materials represent at least two different work functions.
A method of fabricating a field effect transistor comprising the steps of:
A method of making field effect transistors on a wafer having a plurality of predetermined threshold voltages, comprising:
Dependencies are inferred from the claim text.