Power semiconductor devices having laterally extending base shielding regions that inhibit base reach through and methods of forming same

A vertical power device, comprising:

• a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate, said transition region having a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface;
• an insulated gate electrode that extends on the first surface and has first and second opposing ends;
• first and second base regions of second conductivity type that are self-aligned to the first and second ends of said insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of said transition region extending adjacent the first surface;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• and
• first and second base shielding regions of second conductivity type that are more highly doped than said first and second base regions and extend laterally towards each other in said semiconductor substrate to thereby constrict a neck of the upper portion of said transition region to a minimum width at a second depth relative to the first surface.

A vertical power device, comprising:

• a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate and has a vertical doping profile therein that peaks at a first depth relative to the first surface;
• an insulated gate electrode that extends on the first surface and has first and second opposing ends;
• first and second base regions of second conductivity type that are self-aligned to the first and second ends of said insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of said transition region extending adjacent the first surface;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• and
• first and second base shielding regions of second conductivity type that are more highly doped than said first and second base regions and extend laterally towards each other in said semiconductor substrate to thereby constrict a neck of the upper portion of said transition region to a minimum width at about the first depth relative to the first surface.

A vertical power device, comprising:

• a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate and has a vertical doping profile that peaks at a first depth relative to the first surface;
• an insulated gate electrode that extends on a portion of the first surface located opposite an upper portion of said transition region;
• first and second regions of second conductivity type that are self-aligned to first and second opposing ends of said insulated gate electrode, respectively, form respective P-N junctions with opposing sides of said transition region and constrict a neck of the upper portion of said transition region to a minimum width at a second depth relative to the first surface that is greater than about 0.25 microns;
• and
• first and second source regions of first conductivity type in said first and second regions of second conductivity type, respectively.

A vertical power device, comprising:

• a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate;
• an insulated gate electrode that extends on the first surface and has first and second opposing ends;
• first and second base regions of second conductivity type that are self-aligned to the first and second ends of said insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of said transition region extending adjacent the first surface;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• and
• first and second base shielding regions of second conductivity type that are more highly doped than said first and second base regions and extend laterally towards each other in said semiconductor substrate to thereby constrict a neck of the upper portion of said transition region to a minimum width at a first depth relative to the first surface.

A vertical power device, comprising:

• a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of said semiconductor substrate;
• an insulated gate electrode that extends on a portion of the first surface located opposite an upper portion of said transition region;
• first and second regions of second conductivity type that are self-aligned to first and second opposing ends of said insulated gate electrode, respectively, form respective P-N junctions with opposing sides of said transition region and constrict a neck of the upper portion of said transition region to a minimum width at a first depth relative to the first surface that is greater than about 0.25 microns;
• and
• first and second source regions of first conductivity type in said first and second regions of second conductivity type, respectively.

A method of forming a vertical power device, comprising the steps of:

• forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate and has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface;
• forming a gate electrode on the first surface;
• implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;
• annealing the semiconductor substrate to partially drive the base shielding region dopants vertically into the transition region and laterally underneath the gate electrode and thereby define first and second intermediate shielding regions;
• implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the first and second intermediate shielding regions, using the gate electrode as an implant mask;
• annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the upper portion of the transition region to a minimum width;
• and
• forming first and second source regions in the first and second base regions, respectively.

A method of forming a vertical power device, comprising the steps of:

• forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate;
• forming a gate electrode on the first surface;
• implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;
• annealing the semiconductor substrate to partially drive the base shielding region dopants vertically into the transition region and laterally underneath the gate electrode and thereby define first and second intermediate shielding regions;
• implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the first and second intermediate shielding regions, using the gate electrode as an implant mask;
• annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the upper portion of the transition region to a minimum width;
• and
• forming first and second source regions in the first and second base regions, respectively.

A vertical power device, comprising:

• a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;
• first and second insulated electrodes in the first and second trenches;
• first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;
• and
• a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the surface.

A vertical power device, comprising:

• a semiconductor substrate;
• a drift region of first conductivity type in said semiconductor substrate;
• first and second spaced-apart base regions of second conductivity type in said semiconductor substrate;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to a surface of said semiconductor substrate;
• and
• an insulated gate electrode that extends on the surface and opposite said first base region and said transition region.

A vertical power device, comprising:

• a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;
• first and second insulated electrodes in the first and second trenches, respectively;
• a first base region of second conductivity type that extends opposite a sidewall of the first trench and in the mesa;
• a first shielding region of second conductivity type that extends opposite the sidewall of the first trench, is more highly doped than said first base region, is disposed between said first base region and the drift region and forms a P-N rectifying junction with the drift region;
• a source region of first conductivity type in said first base region;
• an insulated gate electrode that extends on the mesa and opposite said first base region;
• and
• a source electrode that extends on said source region and is electrically connected to said first and second insulated electrodes.

A vertical power device, comprising:

• a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;
• first and second insulated electrodes in the first and second trenches;
• first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;
• and
• a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate;
• and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×1012 cm−2 and 6.5×1012 cm−2.

A vertical power device, comprising:

• a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;
• first and second insulated electrodes in the first and second trenches;
• first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• a first insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;
• a second insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said second base region;
• a conductive region that extends between said first and second insulated gate electrodes and opposite the mesa;
• and
• a source electrode that is electrically connected to said first and second source regions and to said conductive region.

A method of forming a vertical power device, comprising the steps of:

• implanting transition region dopants of first conductivity type at a first dose level and first energy level into a surface of a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent the surface;
• forming a gate electrode that extends opposite the implanted transition region dopants, on the surface;
• implanting shielding region dopants of second conductivity type at a second dose level and second energy level into the surface, using the gate electrode as an implant mask;
• implanting base region dopants of second conductivity type at a third dose level and third energy level into the surface, using the gate electrode as an implant mask;
• driving the implanted transition, shielding and base region dopants into the substrate to define a transition region that extends in the drift region and has a vertically retrograded first conductivity type doping profile therein relative to the surface, first and second shielding regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith and first and second base regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith;
• and
• implanting source region dopants of first conductivity type into the first and second base regions, using the gate electrode as an implant mask.

A method of forming a vertical power device, comprising the steps of:

• forming a trench in a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent a sidewall of the trench;
• lining the trench with a trench insulating layer;
• forming a trench-based electrode on the trench insulating layer;
• forming an insulated gate electrode on a surface of the substrate;
• forming a base region of second conductivity type that extends in the substrate and to the sidewall of the trench;
• forming a source region of first conductivity type that extends in the base region and to the sidewall of the trench;
• etching back the trench insulating layer to expose portions of the base and source regions that extend along the sidewall of the trench;
• and
• forming a source contact that is electrically connected to the base and source regions along the sidewall of the trench.

An integrated power device having active and dummy cells therein, comprising:

• a semiconductor substrate a drift region of first conductivity type therein;
• first, second, third and fourth trenches spaced-apart trenches in said semiconductor substrate, said first and second trenches defining an active mesa therebetween into which the drift region extends, said second and third trenches defining a first dummy mesa therebetween into which the drift region extends and said third and fourth trenches defining a second dummy mesa therebetween into which the drift region extends;
• first, second, third and fourth insulated electrodes in said first, second, third and fourth trenches, respectively;
• first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;
• first and second source regions of first conductivity type in said first and second base regions, respectively;
• an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;
• and
• a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate;
• and
• wherein the first and second dummy mesas are devoid of a forward on-state current path.