Method of fabricating a flash memory cell
AssigneeAMIC Technology Corporation
InventorKuo-Yu Chou
Life of this patent
Estimating the term…
Abstract
A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.
Claims17
A method of fabricating a flash memory cell to that utilizes point discharge to reduce the an operation voltage of erasing, the method comprising:
- providing a semiconductor substrate;
- performing an etching process to remove portions of the semiconductor substrate to form at least one V-shape structure in the semiconductor substrate;
- performing a first ion implantation process to form a first doping region around the V-shape structure;
- forming a first dielectric layer on the surfaces of the semiconductor substrate and the first doping region;
- forming a floating gate on the first dielectric layer over the first doping region;
- forming a second dielectric layer on the floating gate;
- forming a controlling gate on the second dielectric layer, a side of the controlling gate being positioned on the semiconductor substrate adjacent to the floating gate;
- and
- performing a second ion implantation process ustilizing the controlling gate as a mask to form at least one a second doping region in the semiconductor substrate.
A method of fabricating a split-gate flash memory cell on a semiconductor substrate, the semiconductor substrate comprising a (100) surface and at least two (111) planes, a silicon oxide layer being positioned on the semiconductor substrate, the method comprising:
- performing a photolithographic and etching processes to form an opening in the silicon oxide layer, the opening connecting to the surface of the semiconductor substrate;
- performing an etching process along the opening, the etching process having a predetermined etching selectivity of the (100) surface to the (111) planes and forming a V-shape structure in the semiconductor substrate;
- forming a first doping region in the semiconductor substrate to surround the V-shape structure;
- forming a first dielectric layer on the semiconductor substrate, followed by forming a floating gate on the first dielectric layer over the first doping region;
- forming a second dielectric layer on the floating gate;
- forming a controlling gate on the second dielectric layer and on the semiconductor substrate adjacent to the floating gate;
- and
- forming a second doping region in the semiconductor substrate adjacent to the controlling gate to complete the fabrication of the split-gate flash memory cell.
Dependencies are inferred from the claim text.