US 2002/0177266 A1Published application

Selectable output edge rate control

OwnerChristian Klein, Myron J. Miskeinventors

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Abstract

A circuit using current starved pull up and pull down transistors is arranged to connect a current source via each transistors to an output transistor stage. The current source values are selected so that the starved transistors provide a known voltage edge rate profile as a function of the current sources and the parameters of the transistors. Two or more additional current sources, that when enabled contribute current in parallel with the first current sources such that controlled edge rate profiles are selectively speeded up in response the enabled current sources. An enable input is provided for each additional current source for selectably controlling the faster or slower edge rate profiles. Reference voltages are used to determine the current source values along with transistor parameters. Preferably the transistor are MOSFETs.

Claims13

Dependent claims

A circuit comprising:

an inverter defining a first input and first output and two states,
a first state with an on pull up transistor and a second state with an on pull down transistor,
a first current source connected to the pull up transistor and a second current source connected to the pull down transistor, wherein when in the first state the first current source provides current to the output, and in the second state the second current source provides current to the first output,
a third current source in parallel with the first current source and a fourth current source in parallel with the second current source,
means for selectively enabling and disabling the third current source from adding to the first current source,
means for selectively enabling and disabling the fourth current source from adding to the second current source, wherein
the voltage edge rate profiles of the first output are controlled when going positive and negative.

4 more elements

Dependencies are inferred from the claim text.