Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor

A method of fabricating a vertical insulated gate transistor, the method comprising:

• forming a vertical semiconductor pillar with one or more flanks on a semiconductor substrate by anisotropic etching;
• forming a gate dielectric layer on the one or more flanks of the pillar and on the substrate;
• forming a semiconductor block resting on the gate dielectric layer;
• forming a dielectrically isolated semiconductor gate resting on the one or more flanks of the pillar and on the substrate;
• and
• forming dielectric cavities extending partly in the semiconductor block, so as to be positioned between the semiconductor block and the gate dielectric and so as to be facing portions of at least the source and drain regions.

An integrated circuit including a vertical insulated gate transistor comprising:

• a semiconductor substrate;
• a vertical pillar with one of a source and drain regions at the top, and an other of the source and drain regions being situated in the substrate at a periphery of the pillar;
• a gate dielectric layer situated on the flanks of the pillar and on the substrate;
• a semiconductor gate resting on the gate dielectric layer, wherein the gate includes a semiconductor block having a first region resting on the gate dielectric layer;
• and
• a second region facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities.