US 2002/0176526 A1 · DATA COMMUNICATIONS BIT STREAM COMBINER/DECOMBINER

Abstract

A method and apparatus for multiplexing and demultiplexing multiple serial data streams provide double the data throughput on a single media channel, such as Fibre Channel (FC). A local clock provides both 0-degree phase and 180-degree phase signals of a clock signal at the same basic frequency as that of the incoming data, as well as a double-frequency clock signal. The first incoming data stream is routed to a first synchronizer unit, which receives a 0-degree phase signal of the local clock. The first synchronizer unit establishes and maintains synchronization of the first data stream with the 0-degree phase signal; it also tags the first data stream by replacing an original fill word with a special fill word. The second incoming data stream, on the other hand, is routed to a second synchronizer unit, which receives a 180-degree phase signal of the local clock. The second synchronizer unit establishes and maintains synchronization of the second data stream with the 180-degree phase signal. The synchronizer units maintain synchronization of the respective data streams by applying an elasticity function to the data streams. After synchronization to the local clock, the two resultant data streams are multiplexed by an interleaver at double the baud rate. At the end of the link, the combined bit streams are demultiplexed into separate bit streams by applying a phase locked loop to the received data, and generating a clock signal at one half of the incoming baud rate. A pattern detector scans the incoming multiplexed data for a fill words. The detector maintains the last received fill word in memory. Each special fill word is replaced with the original fill word. An output router is toggleable so that incoming bits in phase with the special fill words are routed to a first output. All other bits are routed to a second output.

Claims25

Dependent claims

A method for combining first and second incoming serial bit streams having a first baud rate into a single bit stream having a second baud rate with a frequency that is about twice that of said first baud rate, both incoming bit streams organized as frames containing data bits separated by fill words, said method comprising the steps of:

providing a local clock source having a fundamental frequency that is nominally the same as the that of said first baud rate, said local clock source generating a 0°-phase signal at the fundamental frequency, a 180°-phase signal at the fundamental frequency, and a double-frequency signal in phase with both the 0°-phase signal and the 180°-phase signal;
providing first and second synchronizer units, said first synchronizer unit receiving the 0°-phase signal and said first serial bit stream and outputting a reformatted first bit stream synchronized to said 0°-phase signal that contains all the data bits of said first serial bit stream, and said second synchronizer unit receiving the 180°-phase signal and said second serial bit stream and outputting a reformatted second bit stream synchronized to said 180°-phase signal that contains all the data bits of said second serial bit stream;
and
providing an interleaver which receives said reformatted first and second bit streams and combines them both into a single combined bit stream having a baud rate of double said fundamental frequency, and containing all the bits of said reformatted first and second bit streams.

1 more element

A data communications bit stream combiner for combining first and second incoming serial bit streams having a first baud rate into a single bit stream having a second baud rate with a frequency that is about twice that of said first baud rate, both incoming bit streams organized as frames containing data bits separated by fill words, said bit stream combiner comprising:

a local clock source having a fundamental frequency that is nominally the same as the that of said first baud rate, said local clock source generating a 0°-phase signal at the fundamental frequency, a 180°-phase signal at the fundamental frequency, and a double-frequency signal in phase with both the 0°-phase signal and the 180°-phase signal;
first and second synchronizer units, said first synchronizer unit receiving the 0°-phase signal and said first serial bit stream and outputting a reformatted first bit stream synchronized to said 0°-phase signal that contains all the data bits of said first serial bit stream, and said second synchronizer unit receiving the 180°-phase signal and said second serial bit stream and outputting a reformatted second bit stream synchronized to said 180°-phase signal that contains all the data bits of said second serial bit stream;
and
an interleaver which receives said reformatted first and second bit streams and combines them both into a single combined bit stream having a baud rate of double said fundamental frequency, and containing all the bits of said reformatted first and second bit streams.

1 more element

A data communications bit stream combiner for combining 2n number, n being an integer other than zero, of incoming serial bit streams, each of which has a first baud rate, into a single bit stream having a second baud rate having a frequency that is about 2n multiplied by said first baud rate, all incoming bit streams organized as frames containing data bits separated by fill words, said bit stream combiner comprising:

a local clock source having a fundamental frequency that is nominally the same as the that of said first baud rate, said local clock source generating 2n number of equally-spaced-apart, out-of phase clock signals, one of which is in a 0°-phase relationship with said fundamental frequency, and a combining signal having a frequency of the fundamental frequency multiplied by 2n, said combining signal being in phase with each of the equally-spaced-apart clock signals;
2n number of synchronizer units, each synchronizer unit receiving a different incoming serial bit stream and one of said equally-spaced apart clock signals and outputting a reformatted bit stream synchronized to its associated clock signal;
and
an interleaver which receives each of said 2n reformatted bit streams and combines them both into a single combined bit stream having a baud rate of said fundamental frequency multiplied by 2n.

1 more element

Dependencies are inferred from the claim text.

Data communications bit stream combiner/decombiner

Life of this patent

Data communications bit stream combiner/decombiner

Life of this patent

Abstract

Claims25