Apparatus, method and limited set of messages to transmit data between scheduler and a network processor
AssigneeInternational Business Machines Corporation
InventorsJean Louis Calvignac, Marco Heddes, Joseph Franklin Logan
Life of this patent
Estimating the term…
Abstract
An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.
Claims20
A method to communicate comprising the acts of:
- generating in a chip a flow Enqueue.request message having an identification field for carrying indicia to identify a message type, a correlation field carrying a correlator to associate one message with another;
- a frame control block address (FCBA) field to carry a value to be used to reference a packet, a flow queue ID (identification) field to carry a queue number that indicates which flow queue the packet should be placed in, and a discard action field to carry discard information;
- inserting appropriate data in selected fields;
- and
- transmitting the message with the appropriate data.
A device for transporting information comprising:
- a message handler unit including a generator that generates a FlowEnqueue.request message having an identification field for carrying indicia to identify a message type, a correlation field carrying a correlator to associate one message with another;
- a frame control block address (FCBA) to carry a value to be used to reference a packet, a flow queue ID (FQID) to carry a queue number that indicates which flow queue the packet should be placed in, and a discard action field to carry discard information.
A method to communicate comprising the acts of:
- generating, with a transmit controller, a PortStatus.request message having at least a message ID field to carry information identifying the message and port status field to carry information indicating current fill levels of transmit queues;
- loading said PortStatus.request message with appropriate data;
- and
- transmitting said loaded PortStatus.request message.
A device for transporting information including:
- a transmit controller that generates a PortStatus.request request message having a message type ID field to carry information identifying the message;
- and
- a port status field to carry information indicating current filing levels of transmit queues.
A method to communicate comprising the acts of:
- generating a FlowEnqueue.response message having a message ID field to carry information identifying the message;
- a correlator field to carry a correlator and discard acknowledge field to carry a code indicating action taken relative to a packet;
- loading said FlowEnqueue.response message with appropriate data;
- and
- transmitting the loaded FlowEnqueue.response message.
A device for transporting information comprising:
- a flow enqueue controller that generates a FlowEnqueue.response message having a message ID field to carry information identifying the message;
- a correlator field to carry a correlator and discard acknowledge field to carry a code indicating action taken relative to a packet.
A method to communicate including the acts of:
- generating a PortEnqueue.request message having at least message ID field to carry information to identify the message, a frame control block address field to carry information referencing a packet and a port queue ID value specifying in which port queue the packet should be placed;
- loading the PortEnqueue.request message with appropriate data;
- and
- transmitting the loaded PortEnqueue.request message.
A device for transporting information comprising:
- generator for generating a PortEnqueue.request message having at least message ID field to carry information to identify the message, a frame control block address field to carry information referencing a packet and a port queue ID value specifying in which port queue the packet should be placed.
A Network Processor including:
- a receiver controller;
- a data store memory controller operatively coupled to the receive controller;
- a chip-to-chip interface controller;
- a dispatcher operatively coupled to the data store memory controller;
- a plurality of receive queues coupling the receive controller and the dispatcher;
- a completion unit operatively coupled to the chip-to-chip controller;
- EPC coupling the completion unit and the dispatcher;
- a data store access controller coupling the EPC to the data memory controller;
- a plurality of transmit queues operatively coupled to the chip-to-chip interface controller;
- and
- a transmit controller operatively coupled to the transmit queues, data store memory controller and chip-to-chip interface.
Dependencies are inferred from the claim text.